Wednesday, October 29, 2025

OUT 0AH transfers:

 

501. The 8085 has how many hardware interrupts?

A. 3
B. 4
C. 5
D. 6
Answer: C
Explanation:
8085 has 5 hardware interrupts — TRAP, RST7.5, RST6.5, RST5.5, INTR.

502. The highest priority interrupt in 8085 is:

A. RST 7.5
B. RST 6.5
C. TRAP
D. INTR
Answer: C
Explanation:
TRAP is non-maskable and has the highest priority among all interrupts.

503. The lowest priority interrupt in 8085 is:

A. RST 5.5
B. RST 7.5
C. INTR
D. TRAP
Answer: C
Explanation:
INTR is the lowest priority, maskable interrupt.

504. Which interrupt is non-maskable?

A. RST 5.5
B. RST 6.5
C. RST 7.5
D. TRAP
Answer: D
Explanation:
TRAP cannot be disabled by software; it’s non-maskable and edge + level triggered.

505. RST 7.5 is:

A. Edge triggered
B. Level triggered
C. Both edge and level
D. None
Answer: A
Explanation:
RST 7.5 is a positive edge-triggered interrupt.

506. RST 6.5 and RST 5.5 are:

A. Edge triggered
B. Level triggered
C. Both
D. None
Answer: B
Explanation:
RST 6.5 and RST 5.5 are level triggered maskable interrupts.

507. Which interrupt vector address corresponds to RST 7.5?

A. 003CH
B. 0034H
C. 003CH
D. 0030H
Answer: A
Explanation:
Each RST = 8 × N; for RST 7.5, address = 7.5 × 8 = 60 = 3CH.

508. The vector address of RST 6.5 is:

A. 0034H
B. 002CH
C. 003CH
D. 0024H
Answer: A
Explanation:
For RST 6.5 → 6.5 × 8 = 52 = 34H.

509. The EI instruction is used to:

A. Enable all interrupts
B. Disable all interrupts
C. Enable TRAP only
D. Enable RST 7.5 only
Answer: A
Explanation:
EI = Enable Interrupts. It sets the interrupt flip-flop to allow maskable interrupts.

510. The DI instruction is used to:

A. Disable interrupts
B. Enable interrupts
C. Disable only TRAP
D. None
Answer: A
Explanation:
DI = Disable Interrupts → clears the interrupt enable flip-flop.

511. The instruction SIM stands for:

A. Set Interrupt Mask
B. Software Interrupt Mask
C. Set Internal Memory
D. None
Answer: A
Explanation:
SIM controls interrupt masking and serial output via the accumulator bits.

512. The instruction RIM stands for:

A. Read Interrupt Mask
B. Reset Interrupt Mask
C. Read Input Memory
D. None
Answer: A
Explanation:
RIM reads the status of interrupt masks and serial input bit.

513. Which flag is affected by CMP instruction?

A. Carry
B. Zero
C. Sign
D. All of these
Answer: D
Explanation:
CMP affects Carry, Zero, Sign, and Parity flags according to subtraction result.

514. The accumulator contents after XRA A are:

A. 00H
B. FFH
C. A's complement
D. Unchanged
Answer: A
Explanation:
A XOR A = 00H → all flags reset except Zero = 1.

515. The instruction ORA B performs:

A. Bitwise OR
B. Bitwise AND
C. Bitwise XOR
D. Addition
Answer: A
Explanation:
ORA = Bitwise OR between accumulator and register.

516. The instruction ANI 0FH does what?

A. AND accumulator with 0FH
B. OR accumulator with 0FH
C. Add 0FH
D. None
Answer: A
Explanation:
ANI = Logical AND immediate → A = A & 0FH.

517. The instruction ORI 20H means:

A. OR accumulator with 20H
B. AND accumulator with 20H
C. XOR accumulator with 20H
D. Add 20H
Answer: A
Explanation:
ORI performs OR operation with immediate data.

518. Which instruction rotates accumulator left?

A. RAL
B. RLC
C. RAR
D. RRC
Answer: B
Explanation:
RLC rotates accumulator left through carry.

519. RAL differs from RLC by:

A. Including carry in rotation
B. Ignoring carry
C. Rotating right
D. None
Answer: A
Explanation:
RAL rotates accumulator left through carry, while RLC doesn’t use carry.

520. RAR rotates accumulator:

A. Right through carry
B. Left through carry
C. Right without carry
D. Left without carry
Answer: A
Explanation:
RAR = Rotate Accumulator Right through Carry.

521. The instruction PCHL performs:

A. Jump to address in HL pair
B. Push HL to stack
C. Load H and L from PC
D. None
Answer: A
Explanation:
PCHL → Load Program Counter with HL → jump indirectly.

522. The instruction SPHL performs:

A. Load Stack Pointer with HL contents
B. Load HL with SP
C. Swap HL and SP
D. None
Answer: A
Explanation:
SPHL → SP = HL.

523. The instruction XTHL exchanges:

A. HL ↔ Top of stack
B. HL ↔ BC
C. HL ↔ DE
D. HL ↔ Accumulator
Answer: A
Explanation:
XTHL exchanges top two bytes of stack with HL registers.

524. XCHG exchanges:

A. HL and DE
B. BC and DE
C. HL and BC
D. None
Answer: A
Explanation:
XCHG swaps content of HL ↔ DE pairs.

525. How many T-states does MOV A,B require?

A. 4
B. 7
C. 5
D. 10
Answer: A
Explanation:
MOV is a one-byte instruction; requires 4 T-states.

526. How many T-states does LDA 2050H require?

A. 13
B. 10
C. 7
D. 4
Answer: A
Explanation:
LDA is 3-byte instruction → needs 13 T-states.

527. How many T-states does STA 3000H require?

A. 13
B. 10
C. 4
D. 7
Answer: A
Explanation:
STA stores A into given address, 3 bytes → 13 T-states.

528. The instruction IN 05H needs how many bytes?

A. 1
B. 2
C. 3
D. None
Answer: B
Explanation:
IN and OUT are 2-byte I/O operations.

529. OUT 0AH transfers:

A. A → Port 0AH
B. Port 0AH → A
C. HL → Port 0AH
D. None
Answer: A
Explanation:
OUT sends accumulator data to output port address.

530. Stack grows:

A. Upward
B. Downward
C. Fixed
D. Random
Answer: B
Explanation:
In 8085, stack grows downward (higher → lower addresses).

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The instruction DCX SP

 

451. The instruction JNC LABEL performs

A. Jump if carry = 1
B. Jump if carry = 0
C. Jump if zero = 1
D. Jump if zero = 0
Answer: B. Jump if carry = 0
Explanation:
JNC → Jump if No Carry (CY = 0).

452. The instruction JZ LABEL performs

A. Jump if zero flag = 1
B. Jump if zero flag = 0
C. Jump if carry flag = 1
D. Jump always
Answer: A. Jump if zero flag = 1
Explanation:
Used after CMP or arithmetic instructions to check for zero result.

453. The instruction JP LABEL means

A. Jump if positive
B. Jump if parity
C. Jump if program counter set
D. Jump if carry
Answer: A. Jump if positive
Explanation:
JP transfers control if Sign flag = 0 (positive result).

454. The instruction JM LABEL

A. Jump if minus (negative result)
B. Jump if zero
C. Jump if parity
D. Jump always
Answer: A. Jump if minus
Explanation:
JM executes when Sign flag = 1 (result negative).

455. The instruction JPE LABEL

A. Jump if parity even
B. Jump if parity odd
C. Jump if carry
D. Jump always
Answer: A. Jump if parity even
Explanation:
JPE executes when parity flag = 1.

456. The instruction JPO LABEL

A. Jump if parity odd
B. Jump if parity even
C. Jump if zero
D. Jump if carry
Answer: A. Jump if parity odd
Explanation:
JPO executes when parity flag = 0.

457. The instruction JNZ LABEL

A. Jump if zero flag = 0
B. Jump if zero flag = 1
C. Jump if carry flag = 0
D. Jump always
Answer: A. Jump if zero flag = 0
Explanation:
Used to skip or repeat execution if the previous result is non-zero.

458. The instruction SBI data

A. Subtract immediate data with borrow
B. Subtract immediate without borrow
C. Subtract accumulator from data
D. None
Answer: A. Subtract immediate with borrow
Explanation:
SBI subtracts 8-bit immediate data + borrow flag from accumulator.

459. The instruction ACI data performs

A. Add immediate with carry
B. Add immediate without carry
C. Add register pair
D. Add memory
Answer: A. Add immediate with carry
Explanation:
ACI adds 8-bit data and carry flag to accumulator.

460. The instruction XCHG

A. Exchanges contents of DE and HL
B. Exchanges D and H only
C. Exchanges memory and accumulator
D. None
Answer: A. Exchanges contents of DE and HL
Explanation:
XCHG swaps the 16-bit contents of HL and DE register pairs.

461. The instruction SPHL

A. Copies HL to SP
B. Copies SP to HL
C. Exchanges HL and SP
D. None
Answer: A. Copies HL to SP
Explanation:
SPHL → Stack Pointer ← contents of HL.

462. The instruction PCHL

A. Copies HL to PC
B. Copies PC to HL
C. Push HL to stack
D. Pop HL from stack
Answer: A. Copies HL to PC
Explanation:
PCHL → PC ← HL (used for indirect jumps).

463. The instruction XTHL

A. Exchanges top of stack with HL
B. Exchanges SP with HL
C. Pushes HL to stack
D. Pops HL from stack
Answer: A. Exchanges top of stack with HL
Explanation:
Swaps L with (SP) and H with (SP+1).

464. The instruction SIM is used for

A. Serial output and interrupt mask
B. Serial input
C. Interrupt enable
D. Stack operation
Answer: A. Serial output and interrupt mask
Explanation:
SIM → Set Interrupt Mask & Send serial data via SOD.

465. The instruction RIM is used for

A. Read interrupt mask and serial input data
B. Reset interrupt
C. Rotate interrupt
D. Read instruction memory
Answer: A. Read interrupt mask and serial input data
Explanation:
RIM reads interrupt mask status and SID input bit.

466. The READY signal is used for

A. Synchronizing slower peripherals
B. Resetting CPU
C. Interrupt acknowledgment
D. Address decoding
Answer: A. Synchronizing slower peripherals
Explanation:
When READY = 0, CPU waits (inserts wait states) until peripheral is ready.

467. The signal HOLD is used in

A. DMA operation
B. Serial communication
C. Interrupt system
D. Timing control
Answer: A. DMA operation
Explanation:
HOLD requests control of buses for direct memory access.

468. The signal HLDA stands for

A. Hold Acknowledge
B. Halt Data
C. High Data Line Active
D. Hardware Disable Acknowledge
Answer: A. Hold Acknowledge
Explanation:
HLDA is sent by CPU to indicate it granted bus control for DMA.

469. The instruction RST 5 transfers control to address

A. 0028H
B. 0020H
C. 0024H
D. 0030H
Answer: C. 0028H
Explanation:
Restart address = 8 × n; for RST 5 → 8×5 = 40 = 28H.

470. The instruction CALL 2000H takes

A. 3 bytes
B. 2 bytes
C. 1 byte
D. 4 bytes
Answer: A. 3 bytes
Explanation:
Opcode (1 byte) + address (2 bytes) = 3 bytes.

471. The instruction RET takes how many T-states?

A. 6
B. 10
C. 12
D. 16
Answer: C. 10
Explanation:
RET pops 2 bytes from stack to PC (10 T-states).

472. The instruction CALL takes how many T-states?

A. 10
B. 12
C. 18
D. 20
Answer: C. 18
Explanation:
CALL performs stack operations → 18 T-states.

473. The instruction PUSH PSW

A. Pushes accumulator and flag register
B. Pushes only flags
C. Pushes only accumulator
D. Pushes program counter
Answer: A. Pushes accumulator and flag register
Explanation:
PSW = A + Flag register; stored together on stack.

474. The instruction POP PSW

A. Pops accumulator and flag register
B. Pops only flags
C. Pops only accumulator
D. Pops program counter
Answer: A. Pops accumulator and flag register
Explanation:
Restores both A and flag registers from stack memory.

475. The 8085 has how many software interrupts?

A. 5
B. 3
C. 8
D. 6
Answer: A. 5
Explanation:
Software interrupts: RST 0–RST 7 (8 total), but only 5 are reserved for user programs.

476. The hardware interrupts in 8085 are

A. TRAP, RST7.5, RST6.5, RST5.5, INTR
B. RST0–RST7
C. TRAP, INTR only
D. None
Answer: A. TRAP, RST7.5, RST6.5, RST5.5, INTR
Explanation:
These are five hardware interrupt lines available in 8085.

477. The highest priority interrupt in 8085 is

A. TRAP
B. RST 7.5
C. RST 6.5
D. INTR
Answer: A. TRAP
Explanation:
TRAP has the highest priority and is non-maskable.

478. The lowest priority interrupt is

A. RST 5.5
B. RST 6.5
C. RST 7.5
D. INTR
Answer: D. INTR
Explanation:
INTR has the lowest priority among all interrupts.

479. The instruction RLC

A. Rotates accumulator left without carry
B. Rotates accumulator right without carry
C. Rotates left through carry
D. Rotates right through carry
Answer: A. Rotates accumulator left without carry
Explanation:
RLC shifts bits left; D7 moves to D0 and Carry flag.

480. Which interrupt is both level and edge sensitive?

A. TRAP
B. RST7.5
C. RST6.5
D. RST5.5
Answer: A. TRAP
Explanation:
TRAP responds to both edge and level signals for reliability.

481. The S1 and S0 signals in 8085 indicate

A. Type of machine cycle
B. Status of flags
C. Stack operation
D. None
Answer: A. Type of machine cycle
Explanation:
Used to identify opcode fetch, memory read/write, etc.

482. The instruction LHLD 2050H

A. Loads H and L directly from memory 2050H and 2051H
B. Loads H only
C. Loads L only
D. Loads accumulator
Answer: A. Loads H and L directly from memory
Explanation:
Loads L ← (2050H) and H ← (2051H).

483. The instruction SHLD 2050H

A. Stores H and L into memory 2050H and 2051H
B. Stores accumulator
C. Stores only L
D. Stores only H
Answer: A. Stores H and L into consecutive memory locations.

484. The Interrupt Enable flip-flop is controlled by

A. EI and DI instructions
B. RIM and SIM
C. SID and SOD
D. TRAP only
Answer: A. EI and DI instructions
Explanation:
EI enables and DI disables interrupt flip-flop.

485. The 8085 microprocessor is a

A. 8-bit processor with 16-bit address bus
B. 16-bit processor
C. 4-bit processor
D. 32-bit processor
Answer: A. 8-bit processor with 16-bit address bus
Explanation:
Performs 8-bit data operations and can access 64KB memory.

486. The instruction CMP A

A. Sets all flags to zero
B. Does nothing
C. Compares A with itself → zero flag = 1
D. Resets A
Answer: C. Compares A with itself → zero flag = 1
Explanation:
A – A = 0 → zero flag set.

487. The flag register is of size

A. 8-bit
B. 16-bit
C. 4-bit
D. 6-bit
Answer: A. 8-bit
Explanation:
It’s an 8-bit register, though only 5 bits are used as flags.

488. The accumulator is used for

A. Arithmetic and logic operations
B. Memory addressing
C. Stack operation
D. Timing control
Answer: A. Arithmetic and logic operations
Explanation:
Acts as the main register for ALU operations.

489. The instruction ORA B

A. Performs logical OR between A and B
B. Performs AND
C. Performs subtraction
D. Performs addition
Answer: A. Performs logical OR
Explanation:
Result stored in accumulator.

490. The instruction ANA B

A. AND accumulator with B
B. OR accumulator with B
C. Add accumulator with B
D. None
Answer: A. AND accumulator with B
Explanation:
Performs bitwise AND.

491. The instruction SUI 01H

A. Subtract immediate data 01H
B. Add immediate
C. AND immediate
D. None
Answer: A. Subtract immediate
Explanation:
SUI subtracts 8-bit immediate value from accumulator.

492. The instruction MOV M, B

A. Copies content of B into memory (HL)
B. Copies memory into B
C. Copies A into memory
D. Copies B into A
Answer: A. Copies B into memory
Explanation:
Moves data from register B to memory at address (HL).

493. The instruction LDAX B

A. Loads accumulator with content of memory at (BC)
B. Loads accumulator with (DE)
C. Loads B with (A)
D. Loads memory with A
Answer: A. Loads accumulator with (BC)
Explanation:
Indirect addressing mode using register pair BC.

494. The instruction STAX D

A. Stores accumulator at memory (DE)
B. Stores accumulator at (BC)
C. Stores A in D
D. Stores D in A
Answer: A. Stores accumulator at memory (DE).

495. The instruction CPI 00H

A. Compares A with zero
B. Clears A
C. Adds zero to A
D. None
Answer: A. Compares A with zero
Explanation:
Subtracts 00H from A and sets flags accordingly.

496. The instruction MOV B, M

A. Moves memory content to B
B. Moves B to memory
C. Moves A to memory
D. Moves memory to A
Answer: A. Moves memory content to B
Explanation:
B ← (HL).

497. The instruction LDA 2500H

A. Loads A from memory 2500H
B. Loads memory with A
C. Loads A with 25H
D. Loads A with 00H
Answer: A. Loads accumulator with content from 2500H
Explanation:
Direct addressing mode.

498. The instruction STA 2500H

A. Stores accumulator at memory 2500H
B. Loads accumulator
C. Adds A to 2500H
D. None
Answer: A. Stores accumulator at 2500H
Explanation:
Direct memory addressing.

499. The instruction INX SP

A. Increments stack pointer by 1
B. Increments by 2
C. Decrements stack pointer
D. None
Answer: B. Increments by 2
Explanation:
INX operates on 16-bit pairs; increases SP by 2.

500. The instruction DCX SP

A. Decrements stack pointer by 2
B. Decrements by 1
C. Increments SP
D. None
Answer: A. Decrements stack pointer by 2
Explanation:
DCX reduces the 16-bit content of SP by 1 word (2 bytes).

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The microprocessor 8085 operates on a supply voltage of

 

401. The microprocessor 8085 operates on a supply voltage of

A. +12 V
B. +10 V
C. +5 V
D. +3.3 V
Answer: C. +5 V
Explanation:
8085 requires a single +5V DC power supply for operation.

402. The frequency of the internal clock of 8085 is

A. Equal to the crystal frequency
B. Half of the crystal frequency
C. Double the crystal frequency
D. One-fourth of the crystal frequency
Answer: B. Half of the crystal frequency
Explanation:
The internal clock frequency = (external crystal frequency) ÷ 2.

403. The signal INTA̅ stands for

A. Interrupt Accepted
B. Interrupt Acknowledge
C. Internal Transfer
D. Input Acknowledge
Answer: B. Interrupt Acknowledge
Explanation:
INTA̅ is used by 8085 to acknowledge the receipt of an interrupt request.

404. The size of the program counter in 8085 is

A. 8-bit
B. 12-bit
C. 16-bit
D. 20-bit
Answer: C. 16-bit
Explanation:
The PC holds 16-bit address of the next instruction.

405. The maximum addressable memory in 8085 is

A. 8 KB
B. 16 KB
C. 32 KB
D. 64 KB
Answer: D. 64 KB
Explanation:
With 16-bit address lines, 8085 can access 216=65,5362^{16} = 65,536 bytes = 64 KB.

406. The instruction MOV M, A requires how many T-states?

A. 4
B. 7
C. 10
D. 13
Answer: B. 7
Explanation:
It requires one memory write cycle → total 7 T-states.

407. The opcode fetch machine cycle takes

A. 4 T-states
B. 6 T-states
C. 7 T-states
D. 10 T-states
Answer: C. 7 T-states
Explanation:
Opcode fetch cycle is the longest, requiring 7 T-states for 8085.

408. The memory read machine cycle takes

A. 3 T-states
B. 4 T-states
C. 5 T-states
D. 6 T-states
Answer: C. 5 T-states
Explanation:
Memory read and I/O read cycles take 5 T-states in 8085.

409. The instruction STA 2050H requires how many bytes?

A. 1 byte
B. 2 bytes
C. 3 bytes
D. 4 bytes
Answer: C. 3 bytes
Explanation:
Opcode (1 byte) + 16-bit address (2 bytes) = 3 bytes total.

410. The instruction MVI B, 0AH requires how many bytes?

A. 1
B. 2
C. 3
D. 4
Answer: B. 2
Explanation:
Opcode (1 byte) + immediate data (1 byte) = 2 bytes.

411. The instruction INR A affects

A. All flags
B. Carry flag only
C. All except Carry flag
D. None
Answer: C. All except Carry flag
Explanation:
INR changes S, Z, AC, P flags but not Carry.

412. Which instruction is used to restart execution from address 0000H?

A. RST 0
B. RST 1
C. JMP 0000H
D. CALL 0000H
Answer: A. RST 0
Explanation:
RST 0 = CALL 0000H (restart from address 0000H).

413. The signal RESET IN̅

A. Initializes the program counter
B. Resets CPU
C. Restarts system
D. All the above
Answer: D. All the above
Explanation:
RESET IN̅ initializes PC to 0000H and clears registers and flags.

414. The instruction CPI 0AH

A. Compares accumulator with 0AH
B. Adds 0AH to accumulator
C. Loads accumulator with 0AH
D. Clears accumulator
Answer: A. Compares accumulator with 0AH
Explanation:
CPI subtracts 8-bit immediate data from accumulator and sets flags (no change in A).

415. The microprocessor 8085 has how many pins?

A. 20
B. 30
C. 40
D. 64
Answer: C. 40
Explanation:
8085 is a 40-pin dual in-line package IC.

416. The number of address lines multiplexed with data lines in 8085 is

A. 8
B. 16
C. 12
D. 4
Answer: A. 8
Explanation:
Lower-order address bus (A0–A7) is multiplexed with data bus (D0–D7).

417. The ALE signal is used to

A. Latch the lower byte of the address
B. Enable memory
C. Enable interrupts
D. Select I/O device
Answer: A. Latch the lower byte of the address
Explanation:
ALE separates address from multiplexed lines by latching A0–A7.

418. Which control signal indicates that data is to be written into memory?

A. MEMR̅
B. MEMW̅
C. IOR̅
D. IOW̅
Answer: B. MEMW̅
Explanation:
MEMW̅ = 0 indicates memory write operation is active.

419. Which control signal is used for reading from memory?

A. MEMR̅
B. MEMW̅
C. IOR̅
D. IOW̅
Answer: A. MEMR̅
Explanation:
MEMR̅ (Memory Read) signal indicates that data is being read from memory.

420. The signal RD̅ is active when

A. CPU reads data
B. CPU writes data
C. CPU fetches opcode
D. CPU halts
Answer: A. CPU reads data
Explanation:
RD̅ = 0 when processor is reading data from memory or I/O device.

421. The function of SID pin is

A. Serial input data
B. Serial interrupt disable
C. System initialization data
D. Signal interrupt done
Answer: A. Serial input data
Explanation:
SID is used for serial data input in serial communication.

422. The function of SOD pin is

A. Serial output data
B. Start of data
C. System output disable
D. Stop output data
Answer: A. Serial output data
Explanation:
SOD transmits serial output data bit-by-bit under SIM instruction.

423. The stack pointer is initialized typically by

A. LXI SP, address
B. MOV SP, H
C. PCHL
D. XTHL
Answer: A. LXI SP, address
Explanation:
LXI SP, XXXXH initializes stack pointer with a 16-bit address.

424. The HLT instruction halts CPU until

A. RESET
B. INTERRUPT
C. READY signal
D. Both A and B
Answer: D. Both A and B
Explanation:
CPU resumes operation only on reset or interrupt.

425. The instruction NOP occupies how many bytes?

A. 1
B. 2
C. 3
D. 4
Answer: A. 1
Explanation:
NOP is a single-byte instruction consuming 4 T-states.

426. The instruction IN 00H belongs to which addressing mode?

A. Immediate
B. Direct
C. Register
D. I/O Direct
Answer: D. I/O Direct
Explanation:
IN port uses 8-bit port address directly → I/O direct addressing.

427. The instruction XRA A clears accumulator because

A. XOR of same bits is 0
B. It performs addition
C. It resets A flag
D. It initializes carry
Answer: A. XOR of same bits is 0
Explanation:
XORing a number with itself always results in zero.

428. The signal RST 7.5 is

A. Edge triggered
B. Level triggered
C. Software interrupt
D. Both A and C
Answer: A. Edge triggered
Explanation:
RST 7.5 is edge-triggered; others (6.5, 5.5) are level-triggered.

429. The TRAP interrupt is

A. Non-maskable
B. Maskable
C. Software-based
D. Conditional
Answer: A. Non-maskable
Explanation:
TRAP cannot be disabled and has the highest priority.

430. The instruction ORA M performs

A. OR accumulator with memory
B. AND accumulator with memory
C. XOR accumulator with memory
D. Subtract memory from accumulator
Answer: A. OR accumulator with memory
Explanation:
Performs bitwise OR between accumulator and memory (pointed by HL).

431. What happens when EI instruction is executed?

A. Enables all maskable interrupts
B. Disables all interrupts
C. Enables only TRAP
D. Enables RST 7.5 only
Answer: A. Enables all maskable interrupts
Explanation:
EI makes the processor responsive to all hardware interrupts except TRAP (always enabled).

432. The instruction DCR M

A. Decrements memory content by 1
B. Decrements accumulator
C. Decrements register M
D. Clears memory
Answer: A. Decrements memory content by 1
Explanation:
DCR M accesses memory at HL and decreases its value by 1.

433. The instruction ANI 0FH

A. Performs AND with 0FH
B. Performs OR with 0FH
C. Adds 0FH
D. Subtracts 0FH
Answer: A. Performs AND with 0FH
Explanation:
ANI performs logical AND between accumulator and 8-bit immediate data.

434. The instruction CMA takes how many bytes?

A. 1
B. 2
C. 3
D. 4
Answer: A. 1
Explanation:
Single-byte instruction — complements accumulator in one machine cycle.

435. The instruction RAL uses

A. Carry flag
B. Zero flag
C. Parity flag
D. None
Answer: A. Carry flag
Explanation:
RAL rotates accumulator bits through carry.

436. The instruction RRC rotates bits of accumulator

A. Right without carry
B. Right through carry
C. Left without carry
D. Left through carry
Answer: A. Right without carry
Explanation:
RRC rotates all bits right; D0 moves to D7 and carry flag.

437. The instruction RAR

A. Rotates accumulator right through carry
B. Rotates accumulator left through carry
C. Complements accumulator
D. Resets accumulator
Answer: A. Rotates accumulator right through carry
Explanation:
RAR rotates right considering carry flag as a bit.

438. The instruction ORA A

A. Sets accumulator to 00H
B. Keeps accumulator unchanged
C. Complements accumulator
D. Resets carry flag
Answer: B. Keeps accumulator unchanged
Explanation:
A OR A = A, hence no change.

439. The instruction SUB M

A. Subtracts memory from accumulator
B. Subtracts accumulator from memory
C. Adds memory to accumulator
D. Clears memory
Answer: A. Subtracts memory from accumulator
Explanation:
SUB M performs subtraction using memory addressed by HL.

440. The instruction ADC B performs

A. Add with carry
B. Add without carry
C. Subtract
D. Logical AND
Answer: A. Add with carry
Explanation:
ADC adds register and carry flag to accumulator.

441. The instruction ADI 00H

A. Adds zero to accumulator
B. Clears accumulator
C. Sets accumulator
D. No operation
Answer: A. Adds zero to accumulator
Explanation:
Adding zero keeps accumulator unchanged but affects flags.

442. The instruction INR M takes

A. 4 T-states
B. 7 T-states
C. 10 T-states
D. 13 T-states
Answer: B. 7 T-states
Explanation:
Memory increment/decrement instructions require memory access → 7 T-states.

443. The instruction DAD SP performs

A. HL = HL + SP
B. SP = SP + HL
C. HL = HL + HL
D. SP = SP + SP
Answer: A. HL = HL + SP
Explanation:
DAD adds 16-bit register pair contents to HL.

444. The instruction MOV A, A

A. Does nothing
B. Clears accumulator
C. Sets accumulator
D. Rotates accumulator
Answer: A. Does nothing
Explanation:
Copying A to A results in no change.

445. The instruction INX H

A. Increments HL pair
B. Increments H register
C. Increments L register
D. Increments stack pointer
Answer: A. Increments HL pair
Explanation:
INX increases the 16-bit content of a register pair by one.

446. The instruction DCX H

A. Decrements HL pair
B. Decrements H register
C. Decrements L register
D. Decrements accumulator
Answer: A. Decrements HL pair
Explanation:
DCX subtracts 1 from the 16-bit content of HL pair.

447. The instruction RPE means

A. Return if parity even
B. Return if parity odd
C. Restart program execution
D. Return if carry = 1
Answer: A. Return if parity even
Explanation:
RPE is conditional return instruction that checks the parity flag.

448. The instruction RPO

A. Return if parity odd
B. Return if parity even
C. Restart if carry
D. Return if zero
Answer: A. Return if parity odd
Explanation:
RPO executes return only when parity flag = 0 (odd parity).

449. The instruction CNC address

A. Calls subroutine if no carry
B. Calls subroutine if carry
C. Calls subroutine always
D. Calls subroutine if zero
Answer: A. Calls subroutine if no carry
Explanation:
CNC = Call if No Carry (CY = 0).

450. The instruction CZ address

A. Calls subroutine if zero flag = 1
B. Calls if zero flag = 0
C. Calls always
D. Jumps if zero flag = 0
Answer: A. Calls subroutine if zero flag = 1
Explanation:
CZ is a conditional call instruction that checks zero flag.

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