301. 8085 microprocessor has how many address lines?
A. 8
B. 16
C. 32
D. 12
Answer: B
Explanation:
8085 can address memory locations → 16 address lines (A0–A15).
302. 8085 has how many data lines?
A. 8
B. 16
C. 4
D. 32
Answer: A
Explanation:
It has 8-bit data bus (D0–D7), hence an 8-bit microprocessor.
303. The address bus in 8085 is:
A. Unidirectional
B. Bidirectional
C. Tristate
D. Multiplexed
Answer: A
Explanation:
Address bus carries address from CPU to memory → unidirectional.
304. The data bus in 8085 is:
A. Bidirectional
B. Unidirectional
C. Multiplexed
D. None
Answer: A
Explanation:
Data can flow both to and from the CPU → bidirectional.
305. The program counter (PC) in 8085 is:
A. 16-bit register
B. 8-bit register
C. 12-bit
D. 32-bit
Answer: A
Explanation:
PC holds 16-bit address of next instruction to execute.
306. The stack pointer (SP) is a:
A. 16-bit register
B. 8-bit register
C. Temporary register
D. None
Answer: A
Explanation:
SP points to top of the stack, hence 16-bit (because memory is 16-bit addressable).
307. The instruction PUSH H does what?
A. Decrements SP twice and saves HL pair
B. Increments SP twice and saves HL
C. Saves only H
D. None
Answer: A
Explanation:
Stack grows downward → SP decrements twice before storing data.
308. The instruction POP H does what?
A. Loads HL from stack and increments SP twice
B. Decrements SP twice
C. Pushes HL
D. None
Answer: A
Explanation:
POP retrieves two bytes from stack → SP increments twice.
309. Stack memory grows:
A. Downward (towards lower address)
B. Upward
C. Static
D. None
Answer: A
Explanation:
Each PUSH decreases SP → stack grows downward.
310. The size of the instruction CALL 2050H is:
A. 3 bytes
B. 1 byte
C. 2 bytes
D. 4 bytes
Answer: A
Explanation:
Opcode (1 byte) + 16-bit address (2 bytes) = 3 bytes.
311. The instruction RET performs:
A. Pops program counter from stack
B. Pushes PC to stack
C. Halts execution
D. None
Answer: A
Explanation:
RET retrieves 16-bit return address from stack → resumes program.
312. The flag register in 8085 is:
A. 8-bit register
B. 16-bit
C. 4-bit
D. None
Answer: A
Explanation:
Flag register = 8 bits (S, Z, AC, P, CY + 3 unused bits).
313. How many flags are active in 8085?
A. 5
B. 8
C. 6
D. 4
Answer: A
Explanation:
Five flags: Sign, Zero, Auxiliary Carry, Parity, Carry.
314. Sign flag is set when:
A. MSB of result = 1
B. Result = 0
C. Carry generated
D. Parity even
Answer: A
Explanation:
If D7 = 1, result is negative → Sign flag = 1.
315. Zero flag is set when:
A. Result = 0
B. MSB = 1
C. Carry = 1
D. Parity = 1
Answer: A
Explanation:
Zero flag indicates null result after an operation.
316. Carry flag is set when:
A. Carry or borrow occurs
B. Result = 0
C. Parity = even
D. None
Answer: A
Explanation:
Carry flag set → carry out of MSB in addition or borrow in subtraction.
317. Parity flag is set when:
A. Result has even number of 1s
B. Odd number of 1s
C. Carry occurs
D. None
Answer: A
Explanation:
PF = 1 if even parity, else 0.
318. Auxiliary carry flag is used in:
A. BCD arithmetic
B. Logical operations
C. Stack operations
D. None
Answer: A
Explanation:
AC flag shows carry from D3 → D4 → used by DAA.
319. RST 0 address is:
A. 0000H
B. 0008H
C. 0010H
D. 0038H
Answer: A
Explanation:
Vector address = RST number × 8 → 0 × 8 = 0000H.
320. RST 1 vector address is:
A. 0008H
B. 0010H
C. 0018H
D. 0020H
Answer: A
Explanation:
1 × 8 = 8H.
321. The maximum clock frequency of 8085 is:
A. 3 MHz
B. 5 MHz
C. 10 MHz
D. 12 MHz
Answer: B
Explanation:
8085 typically operates at up to 5 MHz.
322. The crystal frequency used for 8085 is usually:
A. 6 MHz
B. 10 MHz
C. 3 MHz
D. 4 MHz
Answer: A
Explanation:
8085 internal clock = external crystal/2 → 6 MHz gives 3 MHz operation.
323. ALE stands for:
A. Address Latch Enable
B. Address Line Enable
C. Address Logic Encoder
D. None
Answer: A
Explanation:
ALE separates multiplexed address/data bus (AD0–AD7).
324. The purpose of ALE signal is:
A. To latch low-order address bus
B. To enable interrupts
C. To control stack
D. None
Answer: A
Explanation:
ALE used with latch to store A0–A7 during first T-state.
325. The READY signal is used for:
A. Synchronizing slow peripherals
B. Reset operation
C. Power control
D. None
Answer: A
Explanation:
If READY = 0 → 8085 waits → allows interfacing with slow memory/I/O.
326. The HOLD signal is used for:
A. DMA operation
B. Interrupt
C. Reset
D. Clock control
Answer: A
Explanation:
HOLD requests CPU to release bus control for DMA transfer.
327. The signal sent by 8085 to acknowledge HOLD is:
A. HLDA
B. INTA̅
C. ALE
D. None
Answer: A
Explanation:
HLDA (Hold Acknowledge) → CPU acknowledges DMA request.
328. The TRAP interrupt has:
A. Highest priority
B. Lowest priority
C. Same as RST 5.5
D. None
Answer: A
Explanation:
TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR.
329. INTR has:
A. Lowest priority
B. Highest
C. Same as TRAP
D. None
Answer: A
Explanation:
INTR is the lowest-priority interrupt.
330. The signal INTA̅ means:
A. Interrupt Acknowledge
B. Interrupt Active
C. Internal Address
D. None
Answer: A
Explanation:
INTA̅ goes low when CPU accepts INTR interrupt request.
331. Number of hardware interrupts in 8085:
A. 5
B. 3
C. 7
D. 4
Answer: A
Explanation:
TRAP, RST 7.5, 6.5, 5.5, and INTR → 5 total hardware interrupts.
332. The signal SID is used for:
A. Serial input data
B. Serial output data
C. Stack input
D. None
Answer: A
Explanation:
SID = Serial Input Data pin.
333. The signal SOD is used for:
A. Serial Output Data
B. Serial Input
C. Stack pointer
D. None
Answer: A
Explanation:
SOD = Serial Output Data pin.
334. The instruction used to send data serially via SOD:
A. SIM
B. RIM
C. EI
D. None
Answer: A
Explanation:
SIM controls SOD (Serial Output Data).
335. The instruction used to read serial input via SID:
A. RIM
B. SIM
C. EI
D. None
Answer: A
Explanation:
RIM reads SID data bit and interrupt masks.
336. The 8085 microprocessor has how many pins?
A. 40
B. 20
C. 28
D. 48
Answer: A
Explanation:
8085 is a 40-pin IC package.
337. The address range for a 16K memory chip is:
A. 0000H–3FFFH
B. 0000H–1FFFH
C. 4000H–7FFFH
D. 8000H–BFFFH
Answer: A
Explanation:
16K = 16384 bytes = 3FFFH offset from base 0000H.
338. To interface 4K memory, number of address lines required:
A. 12
B. 10
C. 16
D. 8
Answer: A
Explanation:
→ 12 address lines.
339. For 8K memory, address lines required are:
A. 13
B. 12
C. 10
D. 8
Answer: A
Explanation:
→ 13 address lines.
340. Memory-mapped I/O uses how many address lines?
A. 16
B. 8
C. 12
D. None
Answer: A
Explanation:
Memory-mapped I/O is treated as memory → full 16-bit addressing.
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