451. The instruction JNC LABEL performs
A. Jump if carry = 1
B. Jump if carry = 0
C. Jump if zero = 1
D. Jump if zero = 0
Answer: B. Jump if carry = 0
Explanation:
JNC → Jump if No Carry (CY = 0).
452. The instruction JZ LABEL performs
A. Jump if zero flag = 1
B. Jump if zero flag = 0
C. Jump if carry flag = 1
D. Jump always
Answer: A. Jump if zero flag = 1
Explanation:
Used after CMP or arithmetic instructions to check for zero result.
453. The instruction JP LABEL means
A. Jump if positive
B. Jump if parity
C. Jump if program counter set
D. Jump if carry
Answer: A. Jump if positive
Explanation:
JP transfers control if Sign flag = 0 (positive result).
454. The instruction JM LABEL
A. Jump if minus (negative result)
B. Jump if zero
C. Jump if parity
D. Jump always
Answer: A. Jump if minus
Explanation:
JM executes when Sign flag = 1 (result negative).
455. The instruction JPE LABEL
A. Jump if parity even
B. Jump if parity odd
C. Jump if carry
D. Jump always
Answer: A. Jump if parity even
Explanation:
JPE executes when parity flag = 1.
456. The instruction JPO LABEL
A. Jump if parity odd
B. Jump if parity even
C. Jump if zero
D. Jump if carry
Answer: A. Jump if parity odd
Explanation:
JPO executes when parity flag = 0.
457. The instruction JNZ LABEL
A. Jump if zero flag = 0
B. Jump if zero flag = 1
C. Jump if carry flag = 0
D. Jump always
Answer: A. Jump if zero flag = 0
Explanation:
Used to skip or repeat execution if the previous result is non-zero.
458. The instruction SBI data
A. Subtract immediate data with borrow
B. Subtract immediate without borrow
C. Subtract accumulator from data
D. None
Answer: A. Subtract immediate with borrow
Explanation:
SBI subtracts 8-bit immediate data + borrow flag from accumulator.
459. The instruction ACI data performs
A. Add immediate with carry
B. Add immediate without carry
C. Add register pair
D. Add memory
Answer: A. Add immediate with carry
Explanation:
ACI adds 8-bit data and carry flag to accumulator.
460. The instruction XCHG
A. Exchanges contents of DE and HL
B. Exchanges D and H only
C. Exchanges memory and accumulator
D. None
Answer: A. Exchanges contents of DE and HL
Explanation:
XCHG swaps the 16-bit contents of HL and DE register pairs.
461. The instruction SPHL
A. Copies HL to SP
B. Copies SP to HL
C. Exchanges HL and SP
D. None
Answer: A. Copies HL to SP
Explanation:
SPHL → Stack Pointer ← contents of HL.
462. The instruction PCHL
A. Copies HL to PC
B. Copies PC to HL
C. Push HL to stack
D. Pop HL from stack
Answer: A. Copies HL to PC
Explanation:
PCHL → PC ← HL (used for indirect jumps).
463. The instruction XTHL
A. Exchanges top of stack with HL
B. Exchanges SP with HL
C. Pushes HL to stack
D. Pops HL from stack
Answer: A. Exchanges top of stack with HL
Explanation:
Swaps L with (SP) and H with (SP+1).
464. The instruction SIM is used for
A. Serial output and interrupt mask
B. Serial input
C. Interrupt enable
D. Stack operation
Answer: A. Serial output and interrupt mask
Explanation:
SIM → Set Interrupt Mask & Send serial data via SOD.
465. The instruction RIM is used for
A. Read interrupt mask and serial input data
B. Reset interrupt
C. Rotate interrupt
D. Read instruction memory
Answer: A. Read interrupt mask and serial input data
Explanation:
RIM reads interrupt mask status and SID input bit.
466. The READY signal is used for
A. Synchronizing slower peripherals
B. Resetting CPU
C. Interrupt acknowledgment
D. Address decoding
Answer: A. Synchronizing slower peripherals
Explanation:
When READY = 0, CPU waits (inserts wait states) until peripheral is ready.
467. The signal HOLD is used in
A. DMA operation
B. Serial communication
C. Interrupt system
D. Timing control
Answer: A. DMA operation
Explanation:
HOLD requests control of buses for direct memory access.
468. The signal HLDA stands for
A. Hold Acknowledge
B. Halt Data
C. High Data Line Active
D. Hardware Disable Acknowledge
Answer: A. Hold Acknowledge
Explanation:
HLDA is sent by CPU to indicate it granted bus control for DMA.
469. The instruction RST 5 transfers control to address
A. 0028H
B. 0020H
C. 0024H
D. 0030H
Answer: C. 0028H
Explanation:
Restart address = 8 × n; for RST 5 → 8×5 = 40 = 28H.
470. The instruction CALL 2000H takes
A. 3 bytes
B. 2 bytes
C. 1 byte
D. 4 bytes
Answer: A. 3 bytes
Explanation:
Opcode (1 byte) + address (2 bytes) = 3 bytes.
471. The instruction RET takes how many T-states?
A. 6
B. 10
C. 12
D. 16
Answer: C. 10
Explanation:
RET pops 2 bytes from stack to PC (10 T-states).
472. The instruction CALL takes how many T-states?
A. 10
B. 12
C. 18
D. 20
Answer: C. 18
Explanation:
CALL performs stack operations → 18 T-states.
473. The instruction PUSH PSW
A. Pushes accumulator and flag register
B. Pushes only flags
C. Pushes only accumulator
D. Pushes program counter
Answer: A. Pushes accumulator and flag register
Explanation:
PSW = A + Flag register; stored together on stack.
474. The instruction POP PSW
A. Pops accumulator and flag register
B. Pops only flags
C. Pops only accumulator
D. Pops program counter
Answer: A. Pops accumulator and flag register
Explanation:
Restores both A and flag registers from stack memory.
475. The 8085 has how many software interrupts?
A. 5
B. 3
C. 8
D. 6
Answer: A. 5
Explanation:
Software interrupts: RST 0–RST 7 (8 total), but only 5 are reserved for user programs.
476. The hardware interrupts in 8085 are
A. TRAP, RST7.5, RST6.5, RST5.5, INTR
B. RST0–RST7
C. TRAP, INTR only
D. None
Answer: A. TRAP, RST7.5, RST6.5, RST5.5, INTR
Explanation:
These are five hardware interrupt lines available in 8085.
477. The highest priority interrupt in 8085 is
A. TRAP
B. RST 7.5
C. RST 6.5
D. INTR
Answer: A. TRAP
Explanation:
TRAP has the highest priority and is non-maskable.
478. The lowest priority interrupt is
A. RST 5.5
B. RST 6.5
C. RST 7.5
D. INTR
Answer: D. INTR
Explanation:
INTR has the lowest priority among all interrupts.
479. The instruction RLC
A. Rotates accumulator left without carry
B. Rotates accumulator right without carry
C. Rotates left through carry
D. Rotates right through carry
Answer: A. Rotates accumulator left without carry
Explanation:
RLC shifts bits left; D7 moves to D0 and Carry flag.
480. Which interrupt is both level and edge sensitive?
A. TRAP
B. RST7.5
C. RST6.5
D. RST5.5
Answer: A. TRAP
Explanation:
TRAP responds to both edge and level signals for reliability.
481. The S1 and S0 signals in 8085 indicate
A. Type of machine cycle
B. Status of flags
C. Stack operation
D. None
Answer: A. Type of machine cycle
Explanation:
Used to identify opcode fetch, memory read/write, etc.
482. The instruction LHLD 2050H
A. Loads H and L directly from memory 2050H and 2051H
B. Loads H only
C. Loads L only
D. Loads accumulator
Answer: A. Loads H and L directly from memory
Explanation:
Loads L ← (2050H) and H ← (2051H).
483. The instruction SHLD 2050H
A. Stores H and L into memory 2050H and 2051H
B. Stores accumulator
C. Stores only L
D. Stores only H
Answer: A. Stores H and L into consecutive memory locations.
484. The Interrupt Enable flip-flop is controlled by
A. EI and DI instructions
B. RIM and SIM
C. SID and SOD
D. TRAP only
Answer: A. EI and DI instructions
Explanation:
EI enables and DI disables interrupt flip-flop.
485. The 8085 microprocessor is a
A. 8-bit processor with 16-bit address bus
B. 16-bit processor
C. 4-bit processor
D. 32-bit processor
Answer: A. 8-bit processor with 16-bit address bus
Explanation:
Performs 8-bit data operations and can access 64KB memory.
486. The instruction CMP A
A. Sets all flags to zero
B. Does nothing
C. Compares A with itself → zero flag = 1
D. Resets A
Answer: C. Compares A with itself → zero flag = 1
Explanation:
A – A = 0 → zero flag set.
487. The flag register is of size
A. 8-bit
B. 16-bit
C. 4-bit
D. 6-bit
Answer: A. 8-bit
Explanation:
It’s an 8-bit register, though only 5 bits are used as flags.
488. The accumulator is used for
A. Arithmetic and logic operations
B. Memory addressing
C. Stack operation
D. Timing control
Answer: A. Arithmetic and logic operations
Explanation:
Acts as the main register for ALU operations.
489. The instruction ORA B
A. Performs logical OR between A and B
B. Performs AND
C. Performs subtraction
D. Performs addition
Answer: A. Performs logical OR
Explanation:
Result stored in accumulator.
490. The instruction ANA B
A. AND accumulator with B
B. OR accumulator with B
C. Add accumulator with B
D. None
Answer: A. AND accumulator with B
Explanation:
Performs bitwise AND.
491. The instruction SUI 01H
A. Subtract immediate data 01H
B. Add immediate
C. AND immediate
D. None
Answer: A. Subtract immediate
Explanation:
SUI subtracts 8-bit immediate value from accumulator.
492. The instruction MOV M, B
A. Copies content of B into memory (HL)
B. Copies memory into B
C. Copies A into memory
D. Copies B into A
Answer: A. Copies B into memory
Explanation:
Moves data from register B to memory at address (HL).
493. The instruction LDAX B
A. Loads accumulator with content of memory at (BC)
B. Loads accumulator with (DE)
C. Loads B with (A)
D. Loads memory with A
Answer: A. Loads accumulator with (BC)
Explanation:
Indirect addressing mode using register pair BC.
494. The instruction STAX D
A. Stores accumulator at memory (DE)
B. Stores accumulator at (BC)
C. Stores A in D
D. Stores D in A
Answer: A. Stores accumulator at memory (DE).
495. The instruction CPI 00H
A. Compares A with zero
B. Clears A
C. Adds zero to A
D. None
Answer: A. Compares A with zero
Explanation:
Subtracts 00H from A and sets flags accordingly.
496. The instruction MOV B, M
A. Moves memory content to B
B. Moves B to memory
C. Moves A to memory
D. Moves memory to A
Answer: A. Moves memory content to B
Explanation:
B ← (HL).
497. The instruction LDA 2500H
A. Loads A from memory 2500H
B. Loads memory with A
C. Loads A with 25H
D. Loads A with 00H
Answer: A. Loads accumulator with content from 2500H
Explanation:
Direct addressing mode.
498. The instruction STA 2500H
A. Stores accumulator at memory 2500H
B. Loads accumulator
C. Adds A to 2500H
D. None
Answer: A. Stores accumulator at 2500H
Explanation:
Direct memory addressing.
499. The instruction INX SP
A. Increments stack pointer by 1
B. Increments by 2
C. Decrements stack pointer
D. None
Answer: B. Increments by 2
Explanation:
INX operates on 16-bit pairs; increases SP by 2.
500. The instruction DCX SP
A. Decrements stack pointer by 2
B. Decrements by 1
C. Increments SP
D. None
Answer: A. Decrements stack pointer by 2
Explanation:
DCX reduces the 16-bit content of SP by 1 word (2 bytes).
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