Q1: The 8085 is an ______-bit microprocessor.
Options:
A. 4
B. 8
C. 16
D. 32
Answer: B. 8
Explanation:
The 8085 is an 8-bit microprocessor, meaning its data bus is 8 bits wide, and it processes data in 8-bit chunks.
Q2: What is the total size of memory (in KB) that the 8085 microprocessor can directly address?
Options:
A. 32 KB
B. 64 KB
C. 128 KB
D. 256 KB
Answer: B. 64 KB
Explanation:
The 8085 has a 16-bit address bus ($2^{16}$ possible addresses), which translates to $65536$ memory locations, or 64 KB ($1 \text{ KB} = 1024 \text{ bytes}$).
Q3: The $AD_7 - AD_0$ lines in the 8085 are used for:
Options:
A. Only Address
B. Only Data
C. Multiplexed Address and Data
D. Interrupt Signals
Answer: C. Multiplexed Address and Data
Explanation:
The lower 8 bits of the address bus ($A_0-A_7$) are time-multiplexed with the 8-bit data bus ($D_0-D_7$). The ALE ($\text{Address Latch Enable}$) signal is used to de-multiplex them.
Q4: Which of the following is a 16-bit register in the 8085 programming model?
Options:
A. Accumulator (A)
B. B-register
C. Stack Pointer (SP)
D. Flag Register
Answer: C. Stack Pointer (SP)
Explanation:
The Stack Pointer (SP) and the Program Counter (PC) are the two 16-bit registers that hold memory addresses. The others listed are 8-bit registers (A, B) or an 8-bit register where only 5 bits are used for flags.
Q5: The highest priority non-maskable interrupt in the 8085 is:
Options:
A. INTR
B. RST 7.5
C. TRAP
D. RST 6.5
Answer: C. TRAP
Explanation:
TRAP is the highest priority interrupt. It is Non-Maskable (cannot be disabled by any instruction) and is typically reserved for catastrophic events like power failure.
Q6: How many software interrupts are available in the 8085 instruction set?
Options:
A. 4
B. 5
C. 8
D. 16
Answer: C. 8
Explanation:
The software interrupts are the RST $n$ instructions (RST 0, RST 1, ..., RST 7), totaling 8 instructions. Each jumps to a specific pre-defined memory location.
Q7: Which of the following instructions uses the Immediate addressing mode?
Options:
A. MOV A, B
B. LDA 2050H
C. MVI A, 32H
D. ADD B
Answer: C. MVI A, 32H
Explanation:
In Immediate Addressing, the 8-bit or 16-bit data is specified in the instruction itself. MVI (Move Immediate) loads the data 32H directly into the accumulator.
Q8: What does the instruction LDA 2000H do?
Options:
A. Load the contents of register A into memory address 2000H.
B. Load the Accumulator with the contents of memory address 2000H.
C. Load the contents of the Accumulator with the data 2000H.
D. Load the data 2000H into register L.
Answer: B. Load the Accumulator with the contents of memory address 2000H.
Explanation:
LDA (Load Accumulator Direct) transfers the 8-bit content from the memory location specified by the 16-bit address (2000H) into the Accumulator (A).
Q9: The Program Status Word (PSW) in the 8085 consists of:
Options:
A. Program Counter and Stack Pointer
B. Accumulator and Flag Register
C. General Purpose Registers (B, C, D, E, H, L)
D. Instruction Register and Program Counter
Answer: B. Accumulator and Flag Register
Explanation:
The PSW is the combination of the Accumulator (A) (8-bit) and the Flag Register (8-bit) that are pushed onto or popped from the stack using the PUSH PSW and POP PSW instructions.
Q10: Which instruction is used to perform a BCD (Binary Coded Decimal) adjust operation in 8085?
Options:
A. CMP
B. ADD
C. DAA
D. RLC
Answer: C. DAA
Explanation:
The DAA (Decimal Adjust Accumulator) instruction adjusts the content of the Accumulator after an addition or subtraction, to form a valid 8-bit BCD number.
Q11: In the $8085$, the stack grows:
Options:
A. Upwards (from low memory to high memory)
B. Downwards (from high memory to low memory)
C. Stays at a fixed address
D. Grows in a circular fashion
Answer: B. Downwards (from high memory to low memory)
Explanation:
The Stack Pointer (SP) is decremented by two before a PUSH operation (storing two bytes) and incremented by two after a POP operation (retrieving two bytes). This means the stack grows toward lower memory addresses.
Q12: Which instruction is used to exchange the contents of the HL register pair with the top of the stack?
Options:
A. SPHL
B. PUSH H
C. POP H
D. XTHL
Answer: D. XTHL
Explanation:
XTHL (Exchange Top of Stack with H and L) exchanges the content of the L register with the byte at the address pointed to by SP, and the content of the H register with the byte at the address SP+1.
Q13: The status of $IO/\bar{M}$, $S_1$, and $S_0$ signals during an Opcode Fetch machine cycle is:
Options:
A. $\text{IO}/\bar{M}=1$, $S_1=1$, $S_0=0$
B. $\text{IO}/\bar{M}=1$, $S_1=0$, $S_0=1$
C. $\text{IO}/\bar{M}=0$, $S_1=1$, $S_0=1$
D. $\text{IO}/\bar{M}=0$, $S_1=0$, $S_0=1$
Answer: C. $\text{IO}/\bar{M}=0$, $S_1=1$, $S_0=1$
Explanation:
An Opcode Fetch is a memory read operation ($\text{IO}/\bar{M}=0$) for fetching an instruction. The status signals $S_1$ and $S_0$ are both 1 during the Opcode Fetch cycle.
Q14: The machine cycle that takes the maximum number of T-states in the 8085 is:
Options:
A. Memory Read
B. I/O Write
C. Opcode Fetch
D. Memory Write
Answer: C. Opcode Fetch
Explanation:
The Opcode Fetch cycle typically requires 4 T-states (T1, T2, T3, T4) because it involves fetching the instruction, decoding it, and then preparing for the next cycle. Other basic memory/IO operations usually require 3 T-states.
Q15: Which interrupt is level-triggered and can be disabled using the DI instruction?
Options:
A. TRAP
B. RST 7.5
C. INTR
D. Only B and C
Answer: C. INTR
Explanation:
The INTR (Interrupt Request) signal is a maskable (can be disabled by DI) and level-triggered interrupt. RST 7.5 is maskable but edge-triggered. TRAP is non-maskable.
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