251. A K-map with 4 variables has how many cells?
A) 8
B) 12
C) 16
D) 32
Answer: C
Explanation: Each variable doubles combinations → 2⁴ = 16 cells.
252. A 2-input NOR gate is equivalent to
A) NOT(AND)
B) NOT(OR)
C) NOT(NAND)
D) OR(NOT)
Answer: B
Explanation: NOR = complement of OR output.
253. The term “hazard” in combinational logic refers to
A) Power loss
B) Undesired output transition
C) Delay
D) Short circuit
Answer: B
Explanation: Hazard causes temporary unwanted output change due to gate delays.
254. Static-1 hazard occurs when
A) Output should stay 1 but momentarily drops
B) Output stays 0 but spikes to 1
C) Input delay mismatches
D) Gate oscillation
Answer: A
Explanation: When logic delay causes momentary 0 despite expected 1 → static-1 hazard.
255. The minimal SOP form of F = A’B + AB’ + AB is
A) A + B
B) A ⊕ B
C) A + B’
D) A’ + B’
Answer: A
Explanation: F = A(B + B’) + A’B = A + B.
256. A JK flip-flop acts as a T flip-flop when
A) J=K=0
B) J=K=1
C) J=0, K=1
D) J=1, K=0
Answer: B
Explanation: J=K=1 → toggling occurs → same as T flip-flop.
257. The output of an XOR gate with both inputs high is
A) 0
B) 1
C) High impedance
D) Undefined
Answer: A
Explanation: XOR = 1 only for unequal inputs → same inputs → output 0.
258. A 10-bit A/D converter has resolution of 5V full scale. Resolution per step = ?
A) 4.88 mV
B) 5.0 mV
C) 10 mV
D) 0.5 mV
Answer: A
Explanation: (5 / 2¹⁰) = 4.88 mV per step.
259. ROM can be used to implement
A) Combinational logic
B) Sequential logic
C) Memory only
D) None
Answer: A
Explanation: ROM stores truth table → acts as combinational circuit.
260. A BCD counter resets after counting
A) 8
B) 9
C) 10
D) 12
Answer: C
Explanation: BCD counts 0000 to 1001 (10 states).
261. The expression (A+B)(A+C) simplifies to
A) A + BC
B) AB + AC
C) A + B + C
D) AB + C
Answer: A
Explanation: Distributive law → A + BC.
262. The metastable state occurs in
A) Combinational circuits
B) Sequential circuits
C) Amplifiers
D) Decoders
Answer: B
Explanation: Sequential circuits (like FFs) enter metastability when setup/hold violated.
263. The propagation delay of TTL logic is about
A) 1 ns
B) 10 ns
C) 100 ns
D) 1 µs
Answer: B
Explanation: Standard TTL gates: 10 ns typical delay.
264. The output of NAND gate is 0 only when
A) All inputs are 1
B) All inputs are 0
C) Inputs are different
D) One input is 1
Answer: A
Explanation: NAND = NOT(AND); AND=1 when all=1 → NAND=0.
265. The 1’s complement of 101001 is
A) 010110
B) 010101
C) 110110
D) 010110
Answer: A
Explanation: Flip all bits → 010110.
266. A 3-bit ring counter has period =
A) 3
B) 6
C) 8
D) 10
Answer: A
Explanation: Ring counter repeats after n states (equal to FF count).
267. Which is faster: SRAM or DRAM?
A) SRAM
B) DRAM
C) Both same
D) Depends on refresh
Answer: A
Explanation: SRAM uses flip-flops → no refresh → faster access.
268. A 4-to-16 decoder requires
A) 2³ = 8 outputs
B) 4 inputs
C) 16 inputs
D) 16 select lines
Answer: B
Explanation: Decoder converts 4-bit input → 16 unique outputs.
269. The logic function F = A + A’B simplifies to
A) A + B
B) A’ + B
C) A + B’
D) A
Answer: A
Explanation: Absorption law: A + A’B = A + B.
270. The binary equivalent of hexadecimal ‘2F’ is
A) 101011
B) 00101111
C) 111011
D) 010111
Answer: B
Explanation: 2 → 0010, F → 1111 → 00101111₂.
271. The enable input in a multiplexer is used to
A) Select inputs
B) Disable output
C) Control output activation
D) Invert input
Answer: C
Explanation: Enable allows/disables entire MUX operation.
272. The operation of demultiplexer is opposite to
A) Decoder
B) Multiplexer
C) Encoder
D) Comparator
Answer: B
Explanation: MUX → many-to-one, DEMUX → one-to-many.
273. The propagation delay of a ripple counter is proportional to
A) Clock period
B) Number of FFs
C) Gate delay
D) Frequency
Answer: B
Explanation: Delay accumulates across cascaded flip-flops.
274. EEPROM stands for
A) Electrically Erasable Programmable Read Only Memory
B) Electrically Editable Permanent ROM
C) Electronic Erase Permanent ROM
D) None
Answer: A
Explanation: EEPROM can be erased and reprogrammed electrically.
275. 2’s complement representation of –7 in 4-bit form =
A) 0111
B) 1001
C) 1000
D) 1111
Answer: B
Explanation: 7=0111 → invert=1000 → +1=1001.
276. The XOR gate output is high when
A) Both inputs are 0
B) Both inputs are 1
C) Inputs are different
D) Inputs are equal
Answer: C
Explanation: XOR = 1 only for unequal inputs.
277. The main advantage of CMOS logic is
A) Low cost
B) Low power consumption
C) High power
D) Large size
Answer: B
Explanation: CMOS uses complementary transistors → almost zero static power.
278. A 3x8 decoder requires how many enable inputs?
A) 0
B) 1
C) 2
D) 3
Answer: B
Explanation: Typically, decoders have single enable line.
279. The output of D flip-flop changes
A) On clock edge
B) On input change
C) On voltage variation
D) Continuously
Answer: A
Explanation: D FF is edge-triggered → transfers input at clock edge.
280. What is the function of a priority encoder?
A) Encode highest priority input
B) Decode all inputs
C) Store binary data
D) None
Answer: A
Explanation: Priority encoder encodes only highest-priority active input.
281. A K-map group of 8 cells eliminates
A) 1 variable
B) 2 variables
C) 3 variables
D) 4 variables
Answer: C
Explanation: Each grouping of 2ⁿ eliminates n variables → 8=2³ → 3 eliminated.
282. A binary half adder has how many inputs?
A) 1
B) 2
C) 3
D) 4
Answer: B
Explanation: Half adder adds 2 single-bit inputs.
283. A 5-bit DAC produces 32 levels. Full-scale output is 10V. Step size = ?
A) 0.25V
B) 0.31V
C) 0.3125V
D) 0.35V
Answer: C
Explanation: 10 / (32–1) = 0.3125 V per step.
284. The full form of ALU is
A) Arithmetic Logic Unit
B) Arithmetic Link Unit
C) Automatic Logic Unit
D) Advanced Logic Unit
Answer: A
Explanation: ALU performs arithmetic and logic operations.
285. In a 4-bit register, maximum decimal number stored =
A) 15
B) 16
C) 8
D) 7
Answer: A
Explanation: 2⁴–1 = 15 (1111).
286. The Boolean identity A + A’B = ?
A) A + B
B) A’ + B
C) AB
D) A’B
Answer: A
Explanation: Absorption law → A + A’B = A + B.
287. In dynamic RAM, refresh rate is determined by
A) Leakage current
B) Supply voltage
C) Clock speed
D) Temperature
Answer: A
Explanation: Capacitor leakage defines refresh period.
288. What is the maximum number of states in a 4-bit asynchronous counter?
A) 8
B) 10
C) 16
D) 32
Answer: C
Explanation: 2⁴ = 16 possible states.
289. The term setup time refers to
A) Time before clock edge input must be stable
B) Time after clock edge
C) Propagation delay
D) Hold time
Answer: A
Explanation: Setup time = min time input stable before clock.
290. The expression (A + B)(A + B’) simplifies to
A) A
B) B
C) AB
D) A + B
Answer: A
Explanation: Apply distributive → A + BB’ = A + 0 = A.
291. The logic family with lowest noise immunity is
A) ECL
B) TTL
C) CMOS
D) RTL
Answer: D
Explanation: RTL = earliest family → poor noise immunity.
292. The master-slave flip-flop eliminates
A) Race around condition
B) Propagation delay
C) Setup time
D) Power loss
Answer: A
Explanation: Master-slave config avoids multiple toggling → removes race-around.
293. A comparator outputs
A) Sum
B) Equality or inequality
C) Difference
D) Carry
Answer: B
Explanation: Comparator checks if A = B or A > B, etc.
294. The main function of a PLA is
A) Fixed decoder
B) Programmable logic array
C) Memory storage
D) Counter
Answer: B
Explanation: PLA implements custom combinational logic.
295. A counter that counts both up and down is called
A) Ripple counter
B) Johnson counter
C) Up-down counter
D) Ring counter
Answer: C
Explanation: Direction controlled by up/down input.
296. Which flip-flop is known as a bistable multivibrator?
A) RS
B) D
C) JK
D) All of the above
Answer: D
Explanation: All FFs have two stable states → bistable devices.
297. A combinational circuit has
A) Memory
B) No memory
C) Clock input
D) Feedback
Answer: B
Explanation: Output depends only on present inputs, not past states.
298. The Boolean equation for NAND gate is
A) (AB)’
B) (A + B)’
C) A’B’
D) A + B
Answer: A
Explanation: NAND = complement of AND → (AB)’.
299. A DeMorgan equivalent of (A + B)’ is
A) A’ + B’
B) AB
C) A’B’
D) A + B
Answer: C
Explanation: (A + B)’ = A’B’ by DeMorgan’s theorem.
300. The key advantage of using Gray code in shaft encoders is
A) Easier binary conversion
B) Minimal error during transition
C) High speed
D) Simple hardware
Answer: B
Explanation: Only one bit changes between successive states → avoids read errors.
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