251. The instruction ADI 09H belongs to which instruction type?
A. Immediate
B. Register
C. Direct
D. Indirect
Answer: A
Explanation:
ADI is an immediate instruction because the data (09H) is specified in the instruction itself.
252. The instruction LXI H, 2050H belongs to which addressing mode?
A. Immediate
B. Register
C. Direct
D. Register indirect
Answer: A
Explanation:
LXI loads register pair with 16-bit immediate data → immediate addressing.
253. The instruction MOV A, M uses which addressing mode?
A. Register indirect
B. Register direct
C. Immediate
D. Direct
Answer: A
Explanation:
M represents memory addressed by HL → register indirect addressing mode.
254. The instruction STA 2500H uses which addressing mode?
A. Direct
B. Immediate
C. Register indirect
D. Register
Answer: A
Explanation:
STA specifies the exact memory address (2500H) → direct addressing.
255. The instruction MOV A, B uses which addressing mode?
A. Register
B. Immediate
C. Direct
D. Indirect
Answer: A
Explanation:
Data is transferred between two registers directly → register addressing.
256. The instruction MVI A, 32H uses which addressing mode?
A. Immediate
B. Register
C. Direct
D. Register indirect
Answer: A
Explanation:
Immediate data (32H) is specified → immediate addressing.
257. The instruction INR M increments:
A. Memory location pointed by HL
B. Register M
C. Memory address in accumulator
D. None
Answer: A
Explanation:
M refers to memory addressed by HL pair → increments that location.
258. The instruction DCR M decrements:
A. Memory location pointed by HL
B. Register M
C. Accumulator
D. None
Answer: A
Explanation:
DCR M decrements memory contents at address in HL.
259. Which instruction subtracts immediate data from accumulator?
A. SUI data
B. SUB data
C. ADI data
D. None
Answer: A
Explanation:
SUI data performs A ← A − immediate data.
260. The instruction CPI 0AH compares:
A. Accumulator with 0AH
B. Memory with 0AH
C. Register B with 0AH
D. None
Answer: A
Explanation:
CPI data → Compare immediate data with accumulator (A − data).
261. The instruction ANA M performs:
A. AND accumulator with memory
B. OR accumulator with memory
C. Subtract memory from accumulator
D. None
Answer: A
Explanation:
ANA M = logical AND between accumulator and memory location pointed by HL.
262. The instruction ORI 0FH performs:
A. Logical OR with 0FH
B. Logical AND
C. Exclusive OR
D. None
Answer: A
Explanation:
ORI = bitwise OR between accumulator and immediate data.
263. The instruction XRI 0AH performs:
A. XOR between A and 0AH
B. OR
C. AND
D. None
Answer: A
Explanation:
XRI = Exclusive OR between accumulator and immediate data.
264. The instruction ANI 0FH performs:
A. AND A with 0FH
B. OR A with 0FH
C. XOR A with 0FH
D. None
Answer: A
Explanation:
ANI performs logical AND with immediate operand.
265. The instruction MOV M, A copies accumulator to:
A. Memory pointed by HL
B. Memory pointed by DE
C. Stack
D. None
Answer: A
Explanation:
MOV M, A transfers A → [HL].
266. Which of the following is a 3-byte instruction?
A. LDA 2000H
B. MVI A, 05H
C. INX H
D. CMA
Answer: A
Explanation:
LDA has opcode + 16-bit address → total 3 bytes.
267. Which instruction is 1 byte?
A. MOV A, B
B. LDA 2050H
C. MVI A, 0FH
D. LXI H, 2050H
Answer: A
Explanation:
MOV type instructions are single-byte operations.
268. The instruction LHLD 2050H loads:
A. HL pair from memory (2050H, 2051H)
B. HL from register
C. Memory from HL
D. None
Answer: A
Explanation:
LHLD loads L ← [2050H], H ← [2051H].
269. The instruction SHLD 2500H stores:
A. HL pair into 2500H and 2501H
B. HL pair into accumulator
C. A into 2500H
D. None
Answer: A
Explanation:
SHLD stores L → [2500H], H → [2501H].
270. The instruction STA 3000H performs:
A. Stores A into 3000H
B. Loads A from 3000H
C. Adds 3000H
D. None
Answer: A
Explanation:
STA stores accumulator content directly into specified address.
271. The instruction LDA 4000H performs:
A. Loads A from memory 4000H
B. Stores A to 4000H
C. Moves data between registers
D. None
Answer: A
Explanation:
LDA loads accumulator from specified address.
272. The instruction HLT belongs to which group?
A. Machine Control
B. Arithmetic
C. Logical
D. Branching
Answer: A
Explanation:
HLT, NOP, DI, EI are machine control instructions.
273. The instruction STC sets:
A. Carry flag
B. Zero flag
C. Sign flag
D. None
Answer: A
Explanation:
STC sets carry flag = 1.
274. The instruction CMC complements:
A. Carry flag
B. Accumulator
C. Sign flag
D. None
Answer: A
Explanation:
CMC toggles carry flag (0→1 or 1→0).
275. Which instruction transfers program control unconditionally?
A. JMP
B. CALL
C. JC
D. JZ
Answer: A
Explanation:
JMP transfers control to target address without checking flags.
276. The instruction CNC 2000H executes jump if:
A. Carry = 0
B. Carry = 1
C. Zero = 0
D. None
Answer: A
Explanation:
CNC = Call if No Carry → Carry flag = 0.
277. The instruction CC 3000H executes call if:
A. Carry = 1
B. Carry = 0
C. Zero = 1
D. None
Answer: A
Explanation:
CC = Call if Carry set.
278. The instruction CPE 2500H executes call if:
A. Parity = even
B. Parity = odd
C. Carry = 0
D. Zero = 1
Answer: A
Explanation:
CPE → Call if parity flag = 1 (even parity).
279. The instruction CNZ 4000H executes call if:
A. Zero = 0
B. Zero = 1
C. Carry = 0
D. None
Answer: A
Explanation:
CNZ = Call if Not Zero → Z = 0.
280. The instruction CZ 2000H executes call if:
A. Zero = 1
B. Zero = 0
C. Carry = 1
D. None
Answer: A
Explanation:
CZ = Call if Zero set → Z = 1.
281. The instruction JPE 3000H jumps if:
A. Parity flag = 1
B. Parity flag = 0
C. Carry = 1
D. None
Answer: A
Explanation:
JPE = Jump if parity even (PF = 1).
282. The instruction JPO 2500H jumps if:
A. Parity flag = 0
B. Parity flag = 1
C. Carry = 0
D. None
Answer: A
Explanation:
JPO = Jump if parity odd (PF = 0).
283. The instruction JP 2050H jumps if:
A. Sign = 0 (positive)
B. Sign = 1 (negative)
C. Zero = 1
D. None
Answer: A
Explanation:
JP → Jump if positive (S = 0).
284. The instruction JM 2050H jumps if:
A. Sign = 1 (negative)
B. Zero = 0
C. Carry = 1
D. None
Answer: A
Explanation:
JM → Jump if minus (S = 1).
285. The instruction ANA A results in:
A. Accumulator unchanged
B. Accumulator = 0
C. Accumulator = 1
D. None
Answer: A
Explanation:
A AND A = A → no change.
286. The instruction ORA A results in:
A. Accumulator unchanged
B. Accumulator = 0
C. Complement accumulator
D. None
Answer: A
Explanation:
A OR A = A → no change.
287. The instruction XRA A results in:
A. Accumulator = 0
B. Accumulator unchanged
C. Complement accumulator
D. None
Answer: A
Explanation:
A XOR A = 0 → clears accumulator.
288. The DAA instruction modifies:
A. Accumulator after BCD addition
B. Flags only
C. Stack pointer
D. None
Answer: A
Explanation:
DAA adjusts the result of BCD addition into valid decimal form.
289. The RAL instruction affects:
A. Carry flag
B. All flags
C. Only Zero
D. None
Answer: A
Explanation:
RAL updates only Carry flag based on MSB rotation.
290. The instruction RLC copies which bit to Carry flag?
A. D7
B. D0
C. D3
D. None
Answer: A
Explanation:
RLC: MSB (D7) → Carry flag.
291. The instruction RRC copies which bit to Carry flag?
A. D0
B. D7
C. D4
D. None
Answer: A
Explanation:
RRC: LSB (D0) → Carry flag.
292. The instruction PUSH PSW pushes:
A. Accumulator and Flags
B. HL pair
C. DE pair
D. None
Answer: A
Explanation:
PUSH PSW saves A and Flags register on the stack.
293. The instruction POP PSW restores:
A. Accumulator and Flags
B. HL pair
C. SP contents
D. None
Answer: A
Explanation:
POP PSW retrieves A and Flags from stack.
294. The instruction EI enables:
A. Maskable interrupts
B. Non-maskable interrupts
C. Serial I/O
D. None
Answer: A
Explanation:
EI enables all maskable interrupts after next instruction.
295. The instruction SIM is used for:
A. Serial Output and Interrupt Masking
B. Serial Input
C. Timer
D. None
Answer: A
Explanation:
SIM sets interrupt masks and sends data on SOD pin.
296. The instruction RIM reads:
A. Interrupt mask and serial input
B. Serial output
C. Carry flag
D. None
Answer: A
Explanation:
RIM reads interrupt mask bits and SID data bit.
297. The TRAP interrupt is:
A. Non-maskable and edge-triggered
B. Maskable
C. Level-triggered only
D. None
Answer: A
Explanation:
TRAP is non-maskable and both edge & level triggered for reliability.
298. The INTR interrupt requires:
A. External hardware acknowledgement
B. Internal vector
C. No hardware
D. None
Answer: A
Explanation:
INTR needs INTA̅ (interrupt acknowledge) from CPU.
299. The vector address of RST 7.5 is:
A. 003CH
B. 0038H
C. 0040H
D. 002CH
Answer: A
Explanation:
RST 7.5 → 7.5 × 8 = 60 decimal = 3CH.
300. The vector address of RST 6.5 is:
A. 0034H
B. 0038H
C. 0030H
D. 0028H
Answer: A
Explanation:
RST 6.5 → 6.5 × 8 = 52 decimal = 34H.
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