401. The microprocessor 8085 operates on a supply voltage of
A. +12 V
B. +10 V
C. +5 V
D. +3.3 V
Answer: C. +5 V
Explanation:
8085 requires a single +5V DC power supply for operation.
402. The frequency of the internal clock of 8085 is
A. Equal to the crystal frequency
B. Half of the crystal frequency
C. Double the crystal frequency
D. One-fourth of the crystal frequency
Answer: B. Half of the crystal frequency
Explanation:
The internal clock frequency = (external crystal frequency) ÷ 2.
403. The signal INTA̅ stands for
A. Interrupt Accepted
B. Interrupt Acknowledge
C. Internal Transfer
D. Input Acknowledge
Answer: B. Interrupt Acknowledge
Explanation:
INTA̅ is used by 8085 to acknowledge the receipt of an interrupt request.
404. The size of the program counter in 8085 is
A. 8-bit
B. 12-bit
C. 16-bit
D. 20-bit
Answer: C. 16-bit
Explanation:
The PC holds 16-bit address of the next instruction.
405. The maximum addressable memory in 8085 is
A. 8 KB
B. 16 KB
C. 32 KB
D. 64 KB
Answer: D. 64 KB
Explanation:
With 16-bit address lines, 8085 can access bytes = 64 KB.
406. The instruction MOV M, A requires how many T-states?
A. 4
B. 7
C. 10
D. 13
Answer: B. 7
Explanation:
It requires one memory write cycle → total 7 T-states.
407. The opcode fetch machine cycle takes
A. 4 T-states
B. 6 T-states
C. 7 T-states
D. 10 T-states
Answer: C. 7 T-states
Explanation:
Opcode fetch cycle is the longest, requiring 7 T-states for 8085.
408. The memory read machine cycle takes
A. 3 T-states
B. 4 T-states
C. 5 T-states
D. 6 T-states
Answer: C. 5 T-states
Explanation:
Memory read and I/O read cycles take 5 T-states in 8085.
409. The instruction STA 2050H requires how many bytes?
A. 1 byte
B. 2 bytes
C. 3 bytes
D. 4 bytes
Answer: C. 3 bytes
Explanation:
Opcode (1 byte) + 16-bit address (2 bytes) = 3 bytes total.
410. The instruction MVI B, 0AH requires how many bytes?
A. 1
B. 2
C. 3
D. 4
Answer: B. 2
Explanation:
Opcode (1 byte) + immediate data (1 byte) = 2 bytes.
411. The instruction INR A affects
A. All flags
B. Carry flag only
C. All except Carry flag
D. None
Answer: C. All except Carry flag
Explanation:
INR changes S, Z, AC, P flags but not Carry.
412. Which instruction is used to restart execution from address 0000H?
A. RST 0
B. RST 1
C. JMP 0000H
D. CALL 0000H
Answer: A. RST 0
Explanation:
RST 0 = CALL 0000H (restart from address 0000H).
413. The signal RESET IN̅
A. Initializes the program counter
B. Resets CPU
C. Restarts system
D. All the above
Answer: D. All the above
Explanation:
RESET IN̅ initializes PC to 0000H and clears registers and flags.
414. The instruction CPI 0AH
A. Compares accumulator with 0AH
B. Adds 0AH to accumulator
C. Loads accumulator with 0AH
D. Clears accumulator
Answer: A. Compares accumulator with 0AH
Explanation:
CPI subtracts 8-bit immediate data from accumulator and sets flags (no change in A).
415. The microprocessor 8085 has how many pins?
A. 20
B. 30
C. 40
D. 64
Answer: C. 40
Explanation:
8085 is a 40-pin dual in-line package IC.
416. The number of address lines multiplexed with data lines in 8085 is
A. 8
B. 16
C. 12
D. 4
Answer: A. 8
Explanation:
Lower-order address bus (A0–A7) is multiplexed with data bus (D0–D7).
417. The ALE signal is used to
A. Latch the lower byte of the address
B. Enable memory
C. Enable interrupts
D. Select I/O device
Answer: A. Latch the lower byte of the address
Explanation:
ALE separates address from multiplexed lines by latching A0–A7.
418. Which control signal indicates that data is to be written into memory?
A. MEMR̅
B. MEMW̅
C. IOR̅
D. IOW̅
Answer: B. MEMW̅
Explanation:
MEMW̅ = 0 indicates memory write operation is active.
419. Which control signal is used for reading from memory?
A. MEMR̅
B. MEMW̅
C. IOR̅
D. IOW̅
Answer: A. MEMR̅
Explanation:
MEMR̅ (Memory Read) signal indicates that data is being read from memory.
420. The signal RD̅ is active when
A. CPU reads data
B. CPU writes data
C. CPU fetches opcode
D. CPU halts
Answer: A. CPU reads data
Explanation:
RD̅ = 0 when processor is reading data from memory or I/O device.
421. The function of SID pin is
A. Serial input data
B. Serial interrupt disable
C. System initialization data
D. Signal interrupt done
Answer: A. Serial input data
Explanation:
SID is used for serial data input in serial communication.
422. The function of SOD pin is
A. Serial output data
B. Start of data
C. System output disable
D. Stop output data
Answer: A. Serial output data
Explanation:
SOD transmits serial output data bit-by-bit under SIM instruction.
423. The stack pointer is initialized typically by
A. LXI SP, address
B. MOV SP, H
C. PCHL
D. XTHL
Answer: A. LXI SP, address
Explanation:
LXI SP, XXXXH initializes stack pointer with a 16-bit address.
424. The HLT instruction halts CPU until
A. RESET
B. INTERRUPT
C. READY signal
D. Both A and B
Answer: D. Both A and B
Explanation:
CPU resumes operation only on reset or interrupt.
425. The instruction NOP occupies how many bytes?
A. 1
B. 2
C. 3
D. 4
Answer: A. 1
Explanation:
NOP is a single-byte instruction consuming 4 T-states.
426. The instruction IN 00H belongs to which addressing mode?
A. Immediate
B. Direct
C. Register
D. I/O Direct
Answer: D. I/O Direct
Explanation:
IN port uses 8-bit port address directly → I/O direct addressing.
427. The instruction XRA A clears accumulator because
A. XOR of same bits is 0
B. It performs addition
C. It resets A flag
D. It initializes carry
Answer: A. XOR of same bits is 0
Explanation:
XORing a number with itself always results in zero.
428. The signal RST 7.5 is
A. Edge triggered
B. Level triggered
C. Software interrupt
D. Both A and C
Answer: A. Edge triggered
Explanation:
RST 7.5 is edge-triggered; others (6.5, 5.5) are level-triggered.
429. The TRAP interrupt is
A. Non-maskable
B. Maskable
C. Software-based
D. Conditional
Answer: A. Non-maskable
Explanation:
TRAP cannot be disabled and has the highest priority.
430. The instruction ORA M performs
A. OR accumulator with memory
B. AND accumulator with memory
C. XOR accumulator with memory
D. Subtract memory from accumulator
Answer: A. OR accumulator with memory
Explanation:
Performs bitwise OR between accumulator and memory (pointed by HL).
431. What happens when EI instruction is executed?
A. Enables all maskable interrupts
B. Disables all interrupts
C. Enables only TRAP
D. Enables RST 7.5 only
Answer: A. Enables all maskable interrupts
Explanation:
EI makes the processor responsive to all hardware interrupts except TRAP (always enabled).
432. The instruction DCR M
A. Decrements memory content by 1
B. Decrements accumulator
C. Decrements register M
D. Clears memory
Answer: A. Decrements memory content by 1
Explanation:
DCR M accesses memory at HL and decreases its value by 1.
433. The instruction ANI 0FH
A. Performs AND with 0FH
B. Performs OR with 0FH
C. Adds 0FH
D. Subtracts 0FH
Answer: A. Performs AND with 0FH
Explanation:
ANI performs logical AND between accumulator and 8-bit immediate data.
434. The instruction CMA takes how many bytes?
A. 1
B. 2
C. 3
D. 4
Answer: A. 1
Explanation:
Single-byte instruction — complements accumulator in one machine cycle.
435. The instruction RAL uses
A. Carry flag
B. Zero flag
C. Parity flag
D. None
Answer: A. Carry flag
Explanation:
RAL rotates accumulator bits through carry.
436. The instruction RRC rotates bits of accumulator
A. Right without carry
B. Right through carry
C. Left without carry
D. Left through carry
Answer: A. Right without carry
Explanation:
RRC rotates all bits right; D0 moves to D7 and carry flag.
437. The instruction RAR
A. Rotates accumulator right through carry
B. Rotates accumulator left through carry
C. Complements accumulator
D. Resets accumulator
Answer: A. Rotates accumulator right through carry
Explanation:
RAR rotates right considering carry flag as a bit.
438. The instruction ORA A
A. Sets accumulator to 00H
B. Keeps accumulator unchanged
C. Complements accumulator
D. Resets carry flag
Answer: B. Keeps accumulator unchanged
Explanation:
A OR A = A, hence no change.
439. The instruction SUB M
A. Subtracts memory from accumulator
B. Subtracts accumulator from memory
C. Adds memory to accumulator
D. Clears memory
Answer: A. Subtracts memory from accumulator
Explanation:
SUB M performs subtraction using memory addressed by HL.
440. The instruction ADC B performs
A. Add with carry
B. Add without carry
C. Subtract
D. Logical AND
Answer: A. Add with carry
Explanation:
ADC adds register and carry flag to accumulator.
441. The instruction ADI 00H
A. Adds zero to accumulator
B. Clears accumulator
C. Sets accumulator
D. No operation
Answer: A. Adds zero to accumulator
Explanation:
Adding zero keeps accumulator unchanged but affects flags.
442. The instruction INR M takes
A. 4 T-states
B. 7 T-states
C. 10 T-states
D. 13 T-states
Answer: B. 7 T-states
Explanation:
Memory increment/decrement instructions require memory access → 7 T-states.
443. The instruction DAD SP performs
A. HL = HL + SP
B. SP = SP + HL
C. HL = HL + HL
D. SP = SP + SP
Answer: A. HL = HL + SP
Explanation:
DAD adds 16-bit register pair contents to HL.
444. The instruction MOV A, A
A. Does nothing
B. Clears accumulator
C. Sets accumulator
D. Rotates accumulator
Answer: A. Does nothing
Explanation:
Copying A to A results in no change.
445. The instruction INX H
A. Increments HL pair
B. Increments H register
C. Increments L register
D. Increments stack pointer
Answer: A. Increments HL pair
Explanation:
INX increases the 16-bit content of a register pair by one.
446. The instruction DCX H
A. Decrements HL pair
B. Decrements H register
C. Decrements L register
D. Decrements accumulator
Answer: A. Decrements HL pair
Explanation:
DCX subtracts 1 from the 16-bit content of HL pair.
447. The instruction RPE means
A. Return if parity even
B. Return if parity odd
C. Restart program execution
D. Return if carry = 1
Answer: A. Return if parity even
Explanation:
RPE is conditional return instruction that checks the parity flag.
448. The instruction RPO
A. Return if parity odd
B. Return if parity even
C. Restart if carry
D. Return if zero
Answer: A. Return if parity odd
Explanation:
RPO executes return only when parity flag = 0 (odd parity).
449. The instruction CNC address
A. Calls subroutine if no carry
B. Calls subroutine if carry
C. Calls subroutine always
D. Calls subroutine if zero
Answer: A. Calls subroutine if no carry
Explanation:
CNC = Call if No Carry (CY = 0).
450. The instruction CZ address
A. Calls subroutine if zero flag = 1
B. Calls if zero flag = 0
C. Calls always
D. Jumps if zero flag = 0
Answer: A. Calls subroutine if zero flag = 1
Explanation:
CZ is a conditional call instruction that checks zero flag.
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