41. How many T-states are there in an Opcode Fetch cycle of 8085?
A. 2
B. 4
C. 6
D. 7
Answer: B. 4
Explanation:
An opcode fetch cycle in 8085 consists of 4 T-states (T1–T4).
42. The memory capacity of 8085 is:
A. 64 KB
B. 128 KB
C. 32 KB
D. 1 MB
Answer: A. 64 KB
Explanation:
Because of the 16-bit address bus, memory locations are addressable.
43. The address and data lines are multiplexed in 8085 for:
A. Reducing pins
B. Increasing speed
C. Increasing cost
D. Separate control
Answer: A. Reducing pins
Explanation:
Multiplexing saves IC pins; AD0–AD7 carry both address (T1) and data (T2–T3).
44. The instruction “MOV M, A” means:
A. Copy data from A to memory location pointed by HL
B. Move A to H
C. Move memory to A
D. Move A to B
Answer: A. Copy data from A to memory location pointed by HL
Explanation:
“M” refers to the memory location whose address is held by HL pair.
45. The control signal IO/M’ distinguishes between:
A. Read/Write
B. Memory and I/O operations
C. Data and address
D. ALU and register operation
Answer: B. Memory and I/O operations
Explanation:
IO/M’ = 0 → Memory, IO/M’ = 1 → I/O operation.
46. When the HOLD signal is active, the processor:
A. Continues execution
B. Stops execution and releases buses
C. Resets
D. Waits forever
Answer: B. Stops execution and releases buses
Explanation:
HOLD requests control of buses; CPU releases address/data bus after current cycle.
47. The instruction “JMP 2050H” is a:
A. 1-byte instruction
B. 2-byte instruction
C. 3-byte instruction
D. 4-byte instruction
Answer: C. 3-byte
Explanation:
Opcode (1 byte) + 16-bit address (2 bytes) = 3 bytes.
48. In 8085, conditional jump instructions are of:
A. 1 byte
B. 2 bytes
C. 3 bytes
D. 4 bytes
Answer: C. 3 bytes
Explanation:
All conditional jump instructions like JZ, JC are 3 bytes.
49. The instruction “CALL 2450H” means:
A. Jump to subroutine at 2450H
B. Return from 2450H
C. Push PC on stack then jump to 2450H
D. Load A from 2450H
Answer: C. Push PC on stack then jump to 2450H
Explanation:
CALL saves return address (PC) on stack before jumping to the subroutine.
50. RET instruction performs:
A. Return from subroutine
B. Return from interrupt
C. Return and reset flags
D. None
Answer: A. Return from subroutine
Explanation:
RET pops address from stack back to PC.
51. The instruction “RST 5” is equivalent to:
A. CALL 0028H
B. CALL 0020H
C. CALL 0024H
D. CALL 0030H
Answer: C. CALL 0028H
Explanation:
Restart instructions jump to fixed locations: RST n = CALL (n × 8).
52. Which interrupt is non-maskable?
A. RST7.5
B. RST6.5
C. RST5.5
D. TRAP
Answer: D. TRAP
Explanation:
TRAP cannot be disabled; highest priority interrupt.
53. RIM instruction stands for:
A. Read Interrupt Mask
B. Read Interrupt Mode
C. Read Input Memory
D. Random Interrupt Map
Answer: A. Read Interrupt Mask
Explanation:
RIM reads the status of interrupts and serial input data.
54. SIM instruction is used to:
A. Set Interrupt Mask
B. Set Instruction Memory
C. Start Interrupt Mode
D. Set Immediate
Answer: A. Set Interrupt Mask
Explanation:
SIM is used for setting interrupt masks and sending serial output data.
55. 8085 has how many software interrupts?
A. 3
B. 5
C. 8
D. 10
Answer: C. 8
Explanation:
RST0–RST7 are software interrupts in 8085.
56. The TRAP interrupt is:
A. Maskable and level triggered
B. Non-maskable and edge + level triggered
C. Maskable and edge triggered
D. Software controlled
Answer: B. Non-maskable and edge + level triggered
Explanation:
TRAP requires both level and edge signals; ensures safe response to faults.
57. The instruction “ANI 0FH” performs:
A. A OR 0FH
B. A AND 0FH
C. A XOR 0FH
D. Compare A with 0FH
Answer: B. A AND 0FH
Explanation:
ANI performs bitwise AND between accumulator and 8-bit immediate data.
58. Which flag is unaffected by arithmetic operations?
A. Carry
B. Zero
C. Sign
D. Trap
Answer: D. Trap (not a flag)
Explanation:
Carry, Zero, Sign, Parity, and Auxiliary Carry are affected; “Trap” is not a flag.
59. Instruction “ORA C” performs:
A. Logical AND of A and C
B. Logical OR of A and C
C. XOR of A and C
D. Subtract C from A
Answer: B. Logical OR of A and C
Explanation:
ORA performs A ← A OR C.
60. The instruction “CMP B” means:
A. Compare A with B
B. Add A and B
C. Copy A to B
D. Subtract B from A and store in A
Answer: A. Compare A with B
Explanation:
CMP performs (A − B) internally; sets flags without changing A.
61. The instruction “RAR” performs:
A. Rotate accumulator left through carry
B. Rotate accumulator right through carry
C. Reverse accumulator bits
D. None
Answer: B. Rotate accumulator right through carry
Explanation:
RAR shifts bits right, LSB → carry, carry → MSB.
62. What is the function of “DAA” instruction?
A. Decimal adjust accumulator
B. Divide accumulator
C. Decrement accumulator
D. None
Answer: A. Decimal adjust accumulator
Explanation:
DAA converts the result of BCD addition to valid BCD form.
63. The instruction “STC” does:
A. Set carry flag
B. Subtract carry flag
C. Store carry flag
D. Reset carry
Answer: A. Set carry flag
Explanation:
STC sets carry flag to 1 unconditionally.
64. “CMC” instruction means:
A. Clear memory counter
B. Complement carry flag
C. Compare carry
D. None
Answer: B. Complement carry flag
Explanation:
CMC flips carry flag: if 1 → 0, if 0 → 1.
65. Which instruction enables all maskable interrupts?
A. EI
B. DI
C. SIM
D. RIM
Answer: A. EI
Explanation:
EI allows maskable interrupts to be recognized.
66. The 8085 microprocessor uses how many addressing modes?
A. 2
B. 3
C. 4
D. 5
Answer: D. 5
Explanation:
Addressing modes: Immediate, Direct, Register, Register indirect, and Implicit.
67. Which instruction does not require operand?
A. MOV A, B
B. ADD B
C. CMA
D. MVI A, 05H
Answer: C. CMA
Explanation:
CMA acts on accumulator only; no operand required.
68. The instruction “LXI H, 2050H” means:
A. Load 2050H into H
B. Load 2050H into HL pair
C. Move A to HL
D. Jump to 2050H
Answer: B. Load 2050H into HL pair
Explanation:
LXI loads 16-bit data into a register pair.
69. What is the function of Program Counter?
A. Points to next instruction
B. Points to current instruction
C. Holds result of ALU
D. Points to stack top
Answer: A. Points to next instruction
Explanation:
PC always contains address of next instruction to be executed.
70. The Stack Pointer (SP) is initialized using:
A. MVI
B. LXI SP, address
C. MOV SP
D. LDA
Answer: B. LXI SP, address
Explanation:
LXI loads 16-bit immediate address into SP register.
71. Which bus carries data between CPU and memory?
A. Address bus
B. Control bus
C. Data bus
D. Instruction bus
Answer: C. Data bus
Explanation:
Data bus is bidirectional and carries actual data.
72. The instruction “SUI 05H” means:
A. Subtract immediate 05H from accumulator
B. Subtract accumulator from 05H
C. Store 05H in A
D. None
Answer: A. Subtract immediate 05H from accumulator
Explanation:
SUI performs A ← A − data.
73. Which of the following is a machine control instruction?
A. MOV A, B
B. HLT
C. ADD B
D. SUB C
Answer: B. HLT
Explanation:
HLT controls processor state, not data.
74. The signal that indicates a new machine cycle is:
A. ALE
B. IO/M
C. READY
D. HOLD
Answer: A. ALE
Explanation:
ALE pulse occurs at start of every machine cycle.
75. Which instruction transfers control unconditionally?
A. JC
B. JZ
C. JMP
D. JNC
Answer: C. JMP
Explanation:
JMP always transfers control to specified address.
76. The instruction “MOV A, M” performs:
A. Copy memory to A
B. Copy A to memory
C. Move A to register
D. Move M to register B
Answer: A. Copy memory to A
Explanation:
MOV A, M copies data from memory (pointed by HL) to accumulator.
77. Number of address lines required for 4 KB memory is:
A. 8
B. 10
C. 12
D. 16
Answer: C. 12
Explanation:
.
78. “SPHL” instruction does what?
A. SP ← HL
B. HL ← SP
C. Swap SP and HL
D. None
Answer: A. SP ← HL
Explanation:
SPHL copies the content of HL pair into SP.
79. “PCHL” instruction means:
A. PC ← HL
B. HL ← PC
C. PC + HL
D. Jump to HL
Answer: A. PC ← HL
Explanation:
PCHL makes the program counter equal to HL; effectively a jump.
80. Which register pair is used to access stack memory?
A. HL
B. SP
C. BC
D. DE
Answer: B. SP
Explanation:
Stack operations are controlled through Stack Pointer register.
81. During a CALL instruction, the return address is stored:
A. In HL pair
B. In accumulator
C. On stack
D. In PC
Answer: C. On stack
Explanation:
CALL pushes return address on stack before jumping.
82. The instruction “XTHL” performs:
A. Exchange top of stack with HL pair
B. Exchange HL and DE
C. Exchange A and memory
D. None
Answer: A. Exchange top of stack with HL pair
Explanation:
XTHL swaps content of HL pair with top two bytes of stack.
83. The function of “NOP” is:
A. Perform no operation
B. Reset processor
C. Disable interrupt
D. Jump to next instruction
Answer: A. Perform no operation
Explanation:
NOP does nothing except consume 4 T-states.
84. The time required to execute one machine cycle is called:
A. Instruction time
B. Clock period
C. Machine cycle time
D. Bus cycle
Answer: C. Machine cycle time
Explanation:
It is the time between start and end of one machine cycle.
85. The instruction “RLC” rotates:
A. Accumulator left without carry
B. Accumulator left through carry
C. Accumulator right
D. None
Answer: A. Accumulator left without carry
Explanation:
RLC shifts all bits left; MSB copied to LSB and Carry flag.
86. Which instruction subtracts the carry flag also?
A. SUB
B. SUI
C. SBB
D. SBI
Answer: C. SBB
Explanation:
SBB = Subtract register + borrow (carry).
87. The instruction “CPE 2000H” executes jump if:
A. Carry = 1
B. Zero = 1
C. Parity even
D. Parity odd
Answer: C. Parity even
Explanation:
CPE = Call if Parity Even.
88. The total number of pins in 8085 is:
A. 40
B. 24
C. 28
D. 42
Answer: A. 40
Explanation:
8085 microprocessor is a 40-pin dual in-line package.
89. READY signal is used for:
A. Synchronization with slower devices
B. Hold control
C. Power indication
D. Reset indication
Answer: A. Synchronization with slower devices
Explanation:
READY = 0 → CPU waits; READY = 1 → CPU continues.
90. The signal which multiplexes address and data lines is:
A. ALE
B. IO/M
C. READY
D. HOLD
Answer: A. ALE
Explanation:
ALE latches the lower address during T1.
91. The instruction “XOR A” does:
A. Clears accumulator
B. Complements accumulator
C. Sets accumulator to FFH
D. None
Answer: A. Clears accumulator
Explanation:
A XOR A = 00H.
92. Which instruction copies content of memory to accumulator indirectly?
A. MOV A, M
B. LDA
C. LDAX
D. XCHG
Answer: C. LDAX
Explanation:
LDAX loads A with data from memory pointed by BC or DE.
93. The instruction “DAD H” performs:
A. Add HL + HL
B. Add A + HL
C. Add SP + HL
D. None
Answer: A. Add HL + HL
Explanation:
DAD adds the specified register pair to
No comments:
Post a Comment