201. The 8085 microprocessor has how many instruction types?
A. 3
B. 5
C. 7
D. 9
Answer: C
Explanation:
8085 instructions are categorized into 7 groups — Data transfer, Arithmetic, Logical, Branching, Stack, I/O, and Machine control.
202. The address bus of 8085 is:
A. 8-bit unidirectional
B. 16-bit unidirectional
C. 8-bit bidirectional
D. 16-bit bidirectional
Answer: B
Explanation:
8085 has a 16-bit unidirectional address bus for addressing up to 64KB memory.
203. The data bus of 8085 is:
A. 8-bit unidirectional
B. 16-bit bidirectional
C. 8-bit bidirectional
D. 16-bit unidirectional
Answer: C
Explanation:
8085 uses an 8-bit bidirectional data bus for data transfer between CPU and memory/I/O.
204. The clock input frequency of 8085 is divided internally by:
A. 1
B. 2
C. 3
D. 4
Answer: B
Explanation:
The 8085 internally divides the clock input frequency by 2 for its internal timing.
205. The instruction CMP B performs:
A. Compare A and B
B. Add A and B
C. Subtract B from A and store result
D. Exchange A and B
Answer: A
Explanation:
CMP compares register with accumulator by performing (A − B) internally; only flags affected.
206. The instruction XRA A results in:
A. Clears accumulator
B. Complements accumulator
C. Sets carry flag
D. None
Answer: A
Explanation:
A XOR A = 0 ⇒ accumulator cleared, flags reset (except Zero flag set).
207. The instruction ANA B performs:
A. Logical AND between A and B
B. Logical OR
C. Logical XOR
D. None
Answer: A
Explanation:
ANA = AND operation between accumulator and register.
208. The CMA instruction performs:
A. Complement accumulator
B. Clear accumulator
C. Compare accumulator
D. None
Answer: A
Explanation:
CMA complements all bits of the accumulator (1’s complement).
209. The DAA instruction is used after:
A. Binary addition
B. BCD addition
C. Logical AND
D. Subtraction
Answer: B
Explanation:
DAA (Decimal Adjust Accumulator) corrects the result after BCD addition.
210. The instruction RAR means:
A. Rotate Accumulator Right through Carry
B. Rotate Accumulator Right
C. Rotate Accumulator Left through Carry
D. None
Answer: A
Explanation:
RAR → Each bit moves right; LSB → Carry, Carry → MSB.
211. The instruction RAL means:
A. Rotate Accumulator Left through Carry
B. Rotate Left without Carry
C. Rotate Right
D. None
Answer: A
Explanation:
RAL rotates accumulator left through carry bit.
212. The instruction RLC rotates:
A. Left without Carry
B. Left through Carry
C. Right through Carry
D. Right without Carry
Answer: A
Explanation:
RLC rotates accumulator left; MSB → Carry, Carry → LSB.
213. The instruction STAX B stores accumulator content into memory pointed by:
A. BC pair
B. DE pair
C. HL pair
D. None
Answer: A
Explanation:
STAX B → Store A into address contained in BC register pair.
214. The instruction LDAX D loads accumulator from address in:
A. DE pair
B. HL pair
C. BC pair
D. Stack pointer
Answer: A
Explanation:
LDAX D → A ← [DE] (memory pointed by DE).
215. The instruction XCHG exchanges:
A. H ↔ D and L ↔ E
B. A ↔ B
C. D ↔ E
D. H ↔ L
Answer: A
Explanation:
XCHG swaps HL and DE register pairs.
216. The SPHL instruction performs:
A. Copies HL contents to Stack Pointer
B. Copies Stack Pointer to HL
C. Exchange HL with SP
D. None
Answer: A
Explanation:
SP ← HL → transfers HL content to Stack Pointer register.
217. The PUSH H instruction performs:
A. Store HL pair onto stack
B. Store H only
C. Pop from stack
D. None
Answer: A
Explanation:
PUSH H decrements SP by 2 and stores contents of H and L registers.
218. The POP H instruction:
A. Retrieves two bytes from stack to HL
B. Pushes data
C. Jumps to subroutine
D. None
Answer: A
Explanation:
POP H increments SP by 2 and loads data into HL pair.
219. The Stack grows in which direction?
A. Upward (Higher to Lower address)
B. Downward (Higher to Lower address)
C. Random
D. None
Answer: B
Explanation:
In 8085, stack grows downward from higher memory to lower address.
220. The maximum stack memory size in 8085 is:
A. 256 bytes
B. 512 bytes
C. 64 KB
D. 32 KB
Answer: C
Explanation:
Since 8085 supports full 64 KB memory, stack can extend up to that depending on SP initialization.
221. The signal RESET IN̅ is used to:
A. Reset CPU
B. Reset peripherals
C. Both A and B
D. None
Answer: A
Explanation:
RESET IN̅ resets Program Counter and internal registers of CPU.
222. The signal RESET OUT is used to:
A. Reset peripherals
B. Reset CPU
C. Hold CPU
D. None
Answer: A
Explanation:
RESET OUT provides reset signal to other connected peripherals.
223. The signal HOLD indicates:
A. DMA request
B. Interrupt
C. Reset
D. None
Answer: A
Explanation:
HOLD is asserted by DMA controller to take control of buses.
224. The signal HLDA means:
A. Hold Acknowledge
B. Halt Acknowledge
C. Hardware Lock
D. None
Answer: A
Explanation:
HLDA is asserted by CPU in response to HOLD, granting bus control.
225. The READY signal is used for:
A. Synchronizing slower memory/I/O
B. Resetting CPU
C. Holding buses
D. None
Answer: A
Explanation:
READY is used to synchronize CPU with slower peripherals by inserting wait states.
226. The S0 and S1 signals represent:
A. Machine cycle status
B. Address
C. Interrupt
D. None
Answer: A
Explanation:
Status signals S0, S1 identify the current machine cycle.
227. The instruction DI means:
A. Disable Interrupts
B. Disable I/O
C. Disable DMA
D. None
Answer: A
Explanation:
DI disables all maskable interrupts.
228. The instruction NOP takes how many T-states?
A. 1
B. 4
C. 7
D. 10
Answer: B
Explanation:
NOP (No Operation) executes in one machine cycle = 4 T-states.
229. The instruction INX H increments:
A. HL pair
B. H register only
C. Accumulator
D. None
Answer: A
Explanation:
INX H adds 1 to the HL pair as a 16-bit number.
230. The instruction DCX H decrements:
A. HL pair
B. H register only
C. Accumulator
D. None
Answer: A
Explanation:
DCX decrements HL register pair by 1.
231. The CALL instruction requires:
A. 3 bytes
B. 1 byte
C. 2 bytes
D. 4 bytes
Answer: A
Explanation:
CALL includes opcode + 16-bit address → total 3 bytes.
232. On execution of CALL 2000H:
A. Return address is pushed to stack
B. Jump to 2000H
C. Both A and B
D. None
Answer: C
Explanation:
CALL pushes return address and transfers control to 2000H.
233. The RET instruction:
A. Pops return address from stack
B. Pushes address to stack
C. Stops execution
D. None
Answer: A
Explanation:
RET retrieves return address and resumes main program.
234. The instruction RST 4 executes equivalent to:
A. CALL 0020H
B. CALL 0040H
C. CALL 0030H
D. CALL 0050H
Answer: A
Explanation:
RST n = CALL (n×8)H → 4×8 = 32 = 0020H.
235. The 8085 supports how many hardware interrupts?
A. 3
B. 4
C. 5
D. 6
Answer: C
Explanation:
Hardware interrupts: TRAP, RST7.5, RST6.5, RST5.5, INTR = total 5.
236. The software interrupts in 8085 are:
A. 8
B. 5
C. 3
D. None
Answer: A
Explanation:
RST 0 to RST 7 → total 8 software interrupts.
237. The instruction SIM stands for:
A. Set Interrupt Mask
B. Software Interrupt Mask
C. Set Immediate Mode
D. None
Answer: A
Explanation:
SIM sets interrupt masks and controls serial output data.
238. The instruction RIM stands for:
A. Read Interrupt Mask
B. Receive Interrupt Mask
C. Read Interrupt and Serial Input Data
D. None
Answer: C
Explanation:
RIM reads interrupt mask and serial input data (SID).
239. The interrupt with highest priority in 8085 is:
A. RST 7.5
B. TRAP
C. INTR
D. RST 6.5
Answer: B
Explanation:
TRAP has the highest priority and is non-maskable.
240. The lowest priority interrupt in 8085 is:
A. INTR
B. RST 5.5
C. RST 7.5
D. TRAP
Answer: A
Explanation:
INTR has the lowest priority and is maskable.
241. The RST 7.5 interrupt is:
A. Edge triggered
B. Level triggered
C. Both
D. None
Answer: A
Explanation:
RST 7.5 is positive edge-triggered interrupt.
242. The RST 6.5 and RST 5.5 interrupts are:
A. Level triggered
B. Edge triggered
C. Both
D. None
Answer: A
Explanation:
RST 6.5 and 5.5 are level triggered.
243. The instruction HLT stops:
A. CPU operation until interrupt or reset
B. I/O operation
C. Clock
D. None
Answer: A
Explanation:
HLT halts processor until interrupt or reset occurs.
244. The instruction PCHL performs:
A. PC ← HL
B. HL ← PC
C. Exchange PC and HL
D. None
Answer: A
Explanation:
PCHL copies contents of HL into Program Counter.
245. The RST 1 instruction jumps to address:
A. 0008H
B. 0000H
C. 0010H
D. 0018H
Answer: A
Explanation:
RST n = n × 8 → 1 × 8 = 8 = 0008H.
246. Which flag is affected by logical operations but not by arithmetic carry?
A. Carry flag
B. Auxiliary carry flag
C. Zero flag
D. Sign flag
Answer: B
Explanation:
Auxiliary Carry (AC) flag changes during BCD/logical ops, not full carry.
247. The ORA instruction performs:
A. Logical OR
B. Logical AND
C. Exclusive OR
D. None
Answer: A
Explanation:
ORA performs bitwise OR between accumulator and operand.
248. The SUB instruction performs:
A. A ← A − Reg
B. A ← Reg − A
C. A ← A + Reg
D. None
Answer: A
Explanation:
SUB subtracts operand from accumulator.
249. The instruction SBB B performs:
A. Subtract with Borrow
B. Subtract without Borrow
C. Add with Carry
D. None
Answer: A
Explanation:
SBB = Subtract register and Carry flag from accumulator.
250. The instruction ADI 05H affects:
A. All flags
B. Only Zero flag
C. Only Carry flag
D. None
Answer: A
Explanation:
ADI affects all arithmetic flags: CY, Z, S, P, AC.
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