161. The signal ALE stands for:
A. Address Latch Enable
B. Address Load Enable
C. Arithmetic Logic Enable
D. Address Logic Execution
Answer: A
Explanation:
ALE (Address Latch Enable) is used to demultiplex the lower byte of the address (AD0–AD7) from data.
162. In 8085, the lower 8 address lines are multiplexed with:
A. Control bus
B. Data bus
C. Address bus
D. None
Answer: B
Explanation:
AD0–AD7 lines serve as multiplexed Address/Data bus.
163. The size of the program counter in 8085 is:
A. 8-bit
B. 12-bit
C. 16-bit
D. 32-bit
Answer: C
Explanation:
Program Counter (PC) is 16-bit → stores address of next instruction.
164. The memory address of the next instruction is stored in:
A. Stack Pointer
B. Program Counter
C. Accumulator
D. Instruction Register
Answer: B
Explanation:
Program Counter (PC) holds address of next instruction to be fetched.
165. The memory capacity that can be interfaced with 8085 is:
A. 32 KB
B. 64 KB
C. 128 KB
D. 1 MB
Answer: B
Explanation:
16-bit address → = 64 KB addressable memory.
166. The control signal RD̅ is active when:
A. Reading data from memory or I/O
B. Writing to memory
C. Resetting CPU
D. None
Answer: A
Explanation:
RD̅ (Read) signal becomes active low when CPU reads data.
167. The control signal WR̅ is active when:
A. CPU writes data to memory or I/O
B. Reads data
C. Resets CPU
D. None
Answer: A
Explanation:
WR̅ (Write) = active low signal generated when CPU writes data.
168. The IO/M̅ signal differentiates between:
A. Memory and I/O operation
B. Read and Write
C. Address and Data
D. None
Answer: A
Explanation:
IO/M̅ = 0 for memory operations, 1 for I/O operations.
169. The 8085 has how many pins?
A. 30
B. 35
C. 40
D. 42
Answer: C
Explanation:
8085 is a 40-pin DIP (Dual Inline Package) IC.
170. Which signal indicates an instruction fetch operation?
A. IO/M̅ = 0 and S1=1, S0=1
B. IO/M̅ = 1
C. RD̅ = 0
D. WR̅ = 1
Answer: A
Explanation:
Combination IO/M̅=0, S1=1, S0=1 specifies Opcode Fetch machine cycle.
171. How many machine cycles are used in execution of STA 2000H?
A. 3
B. 4
C. 5
D. 6
Answer: C
Explanation:
STA takes 5 cycles: opcode fetch, 2 address fetch, 1 memory write, 1 internal execution.
172. The instruction MOV M, A requires how many T-states?
A. 4
B. 7
C. 10
D. 13
Answer: B
Explanation:
MOV M, A involves memory write → 7 T-states.
173. The instruction MOV A, M requires:
A. 4 T-states
B. 7 T-states
C. 10 T-states
D. 13 T-states
Answer: B
Explanation:
Memory read operation → 7 T-states.
174. The instruction MVI A, 25H requires:
A. 7 T-states
B. 10 T-states
C. 4 T-states
D. 5 T-states
Answer: D
Explanation:
Immediate data fetch = 2-byte instruction → 2 machine cycles = 7 + 3 = 10 T-states.
175. The term "Opcode Fetch" means:
A. Fetching the operation code from memory
B. Fetching data
C. Fetching address
D. None
Answer: A
Explanation:
Opcode Fetch = reading the instruction code from memory to Instruction Register.
176. The clock frequency of 8085 is divided by:
A. 1
B. 2
C. 3
D. 4
Answer: B
Explanation:
8085 internally divides the input clock by 2 to generate internal timing signals.
177. The time taken to complete one operation is called:
A. Machine cycle
B. Instruction cycle
C. T-state
D. None
Answer: A
Explanation:
Machine cycle = time required to complete one basic operation (e.g., memory read).
178. Each machine cycle consists of:
A. 2 T-states
B. 3 T-states
C. 4 to 6 T-states
D. 10 T-states
Answer: C
Explanation:
Each machine cycle typically has 4–6 T-states depending on the instruction.
179. The instruction ADD M requires:
A. 1 machine cycle
B. 2 machine cycles
C. 3 machine cycles
D. 4 machine cycles
Answer: B
Explanation:
Memory read (to fetch M) + execution → 2 machine cycles.
180. The instruction JMP requires:
A. 2 bytes
B. 3 bytes
C. 1 byte
D. 4 bytes
Answer: B
Explanation:
JMP addr includes opcode + 16-bit address → 3 bytes.
181. The instruction ADI 10H is a:
A. Immediate instruction
B. Direct instruction
C. Register instruction
D. None
Answer: A
Explanation:
ADI uses immediate data → Immediate addressing mode.
182. LDA 2000H uses which addressing mode?
A. Direct
B. Immediate
C. Register
D. Indirect
Answer: A
Explanation:
Address is specified directly → Direct addressing.
183. MOV A, B uses which addressing mode?
A. Register
B. Direct
C. Immediate
D. Implicit
Answer: A
Explanation:
Data transferred between registers → Register addressing.
184. MOV A, M uses which addressing mode?
A. Register Indirect
B. Register
C. Direct
D. Immediate
Answer: A
Explanation:
Address of memory given by HL pair → Register Indirect addressing.
185. INR A uses which addressing mode?
A. Register
B. Immediate
C. Direct
D. Implicit
Answer: D
Explanation:
Operand implied (A register) → Implicit addressing.
186. The 8085 uses how many interrupt control instructions?
A. 2
B. 3
C. 4
D. 5
Answer: B
Explanation:
Interrupt control instructions: EI, DI, SIM, RIM → total 4.
187. The flag register in 8085 is:
A. 8-bit
B. 16-bit
C. 4-bit
D. None
Answer: A
Explanation:
Flag register is 8-bit, but only 5 bits used for flags.
188. The instruction RST 7 corresponds to address:
A. 0038H
B. 0030H
C. 0028H
D. 0040H
Answer: A
Explanation:
RST n = n × 8 → 7×8 = 56 = 38H = 0038H.
189. Which register pair is used as memory pointer in 8085?
A. HL
B. DE
C. BC
D. None
Answer: A
Explanation:
HL pair holds 16-bit address → used as memory pointer (M).
190. The instruction OUT 80H transfers:
A. Data from accumulator to I/O port 80H
B. Data from memory to accumulator
C. Data from I/O to accumulator
D. None
Answer: A
Explanation:
OUT sends accumulator data to specified I/O port.
191. The 8085 has how many status signals?
A. 1
B. 2
C. 3
D. 4
Answer: C
Explanation:
Status signals: IO/M̅, S1, S0 — indicate current operation type.
192. The TRAP interrupt is:
A. Non-maskable and edge-triggered
B. Maskable and level-triggered
C. Non-maskable and level-triggered
D. Maskable and edge-triggered
Answer: C
Explanation:
TRAP is non-maskable and edge + level sensitive interrupt.
193. When the 8085 is RESET, the PC is loaded with:
A. 0000H
B. FFFFH
C. 8000H
D. 2000H
Answer: A
Explanation:
Reset initializes PC = 0000H (program execution begins here).
194. The instruction RST 0 is equivalent to:
A. CALL 0000H
B. JMP 0000H
C. CALL 0080H
D. None
Answer: A
Explanation:
RST 0 = software interrupt calling subroutine at 0000H.
195. In 8085, the SID and SOD pins are used for:
A. Serial communication
B. Parallel data transfer
C. Interrupt control
D. Reset
Answer: A
Explanation:
SID (Serial Input Data), SOD (Serial Output Data) used for serial I/O.
196. The HLT instruction can be terminated by:
A. Interrupt or Reset
B. NOP
C. EI instruction
D. CALL instruction
Answer: A
Explanation:
CPU halts until it receives interrupt or reset signal.
197. The 8085 processor supports how many addressing modes?
A. 3
B. 4
C. 5
D. 6
Answer: C
Explanation:
Addressing modes: Immediate, Direct, Register, Register Indirect, and Implicit.
198. The instruction LHLD 2050H loads:
A. L ← [2050H], H ← [2051H]
B. H ← [2050H], L ← [2051H]
C. A ← [2050H]
D. None
Answer: A
Explanation:
LHLD loads 16-bit data from consecutive memory locations into L and H registers.
199. The instruction SHLD 3000H stores:
A. L → 3000H, H → 3001H
B. H → 3000H, L → 3001H
C. A → 3000H
D. None
Answer: A
Explanation:
SHLD stores HL pair contents into specified consecutive memory locations.
200. The function of the instruction EI is:
A. Enable maskable interrupts
B. Enable non-maskable interrupts
C. Disable interrupts
D. None
Answer: A
Explanation:
EI enables all maskable interrupts after the next instruction.
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