11. 8085 microprocessor has how many general purpose registers?
A. 5
B. 6
C. 7
D. 8
Answer: B. 6
Explanation:
Registers B, C, D, E, H, and L are six 8-bit general-purpose registers in 8085.
12. The register pair used as memory pointer in 8085 is:
A. B–C
B. D–E
C. H–L
D. A–F
Answer: C. H–L
Explanation:
H–L register pair holds the 16-bit memory address for data access.
13. The size of program counter in 8085 is:
A. 8-bit
B. 12-bit
C. 16-bit
D. 20-bit
Answer: C. 16-bit
Explanation:
The Program Counter (PC) is a 16-bit register which stores the next instruction address.
14. The instruction “MVI A, 55H” performs:
A. Move 55H to memory
B. Move contents of A to 55H
C. Load immediate data 55H into accumulator
D. Add 55H to accumulator
Answer: C. Load immediate data 55H into accumulator
Explanation:
MVI loads an 8-bit immediate value into the specified register.
15. The content of the accumulator after XRA A instruction is:
A. 00H
B. FFH
C. Same as before
D. Undefined
Answer: A. 00H
Explanation:
XRA A performs A XOR A = 0. Hence accumulator is cleared.
16. Which instruction is used to clear accumulator?
A. CLR A
B. MOV A, 00H
C. XRA A
D. SUB A
Answer: C. XRA A
Explanation:
XRA A results in A XOR A = 0, clearing the accumulator.
17. The instruction “LDA 2050H” means:
A. Load accumulator with contents of memory location 2050H
B. Load accumulator with address 2050H
C. Store accumulator in 2050H
D. None
Answer: A. Load accumulator with contents of memory location 2050H
Explanation:
LDA is a 3-byte instruction that loads data from the given memory address into A.
18. The instruction “STA 2500H” means:
A. Store accumulator contents into memory 2500H
B. Load accumulator from 2500H
C. Add 2500H to accumulator
D. Move A to register
Answer: A. Store accumulator contents into memory 2500H
Explanation:
STA stores the contents of accumulator into specified memory.
19. “INX H” performs:
A. Increment H only
B. Increment L only
C. Increment H–L pair by 1
D. Increment H–L pair by 2
Answer: C. Increment H–L pair by 1
Explanation:
INX increments the 16-bit register pair content by 1.
20. Which instruction is used to exchange H–L and D–E pair contents?
A. EXH
B. XCHG
C. SWAP
D. XRA
Answer: B. XCHG
Explanation:
XCHG swaps data between H–L and D–E register pairs.
21. Which instruction complements accumulator content?
A. CMA
B. CMC
C. CMP
D. CMAA
Answer: A. CMA
Explanation:
CMA inverts all bits of accumulator (1’s complement).
22. The instruction “ADI 09H” performs:
A. Add contents of memory 09H to accumulator
B. Add immediate 09H to accumulator
C. Add register 09H
D. None
Answer: B. Add immediate 09H to accumulator
Explanation:
ADI adds the 8-bit immediate value to accumulator.
23. After executing DCR A, the accumulator value decreases by:
A. 2
B. 1
C. 0
D. Depends on carry
Answer: B. 1
Explanation:
DCR decrements register by 1 without affecting carry flag.
24. The instruction “STA” is a:
A. 1-byte
B. 2-byte
C. 3-byte
D. None
Answer: C. 3-byte
Explanation:
STA = opcode + 16-bit address (3 bytes).
25. The 8085 microprocessor has how many hardware interrupts?
A. 2
B. 3
C. 5
D. 7
Answer: C. 5
Explanation:
8085 has 5 hardware interrupts: TRAP, RST7.5, RST6.5, RST5.5, INTR.
26. Highest priority interrupt in 8085 is:
A. RST7.5
B. INTR
C. TRAP
D. RST5.5
Answer: C. TRAP
Explanation:
TRAP is non-maskable and has the highest priority.
27. The instruction “CPI 0AH” compares accumulator with:
A. 0AH register
B. Immediate data 0AH
C. Memory 0AH
D. Stack top
Answer: B. Immediate data 0AH
Explanation:
CPI subtracts immediate 8-bit data from accumulator (A – data) without changing A.
28. Carry flag is affected by:
A. Logical instructions
B. Arithmetic instructions
C. Data transfer
D. None
Answer: B. Arithmetic instructions
Explanation:
Carry flag reflects overflow in arithmetic operations.
29. When zero flag = 1, it means:
A. Result is zero
B. Result is negative
C. Carry generated
D. Overflow occurred
Answer: A. Result is zero
Explanation:
Zero flag is set when ALU result equals zero.
30. Which instruction disables all maskable interrupts?
A. SIM
B. RIM
C. DI
D. EI
Answer: C. DI
Explanation:
DI (Disable Interrupt) turns off all maskable interrupts.
31. The instruction “PUSH B” does what?
A. Stores B and C on stack
B. Stores only B
C. Stores only C
D. None
Answer: A. Stores B and C on stack
Explanation:
PUSH B pushes the B–C pair (two bytes) onto the stack.
32. Stack in 8085 grows towards:
A. Higher memory addresses
B. Lower memory addresses
C. Random locations
D. None
Answer: B. Lower memory addresses
Explanation:
Stack Pointer decrements with each PUSH operation (stack grows downward).
33. Which instruction pops data from stack into H–L pair?
A. POP H
B. POP B
C. POP D
D. POP P
Answer: A. POP H
Explanation:
POP H retrieves two bytes from stack into H–L pair.
34. The instruction “HLT” means:
A. Halt execution
B. Hold bus
C. Halt memory
D. None
Answer: A. Halt execution
Explanation:
HLT stops program execution until a reset or interrupt occurs.
35. Which signal indicates that 8085 is ready for next operation?
A. READY
B. HOLD
C. ALE
D. IO/M
Answer: A. READY
Explanation:
READY pin ensures synchronization with slower peripherals.
36. ALE stands for:
A. Address Latch Enable
B. Address Logic Enable
C. Arithmetic Logic Execution
D. Address Load Enable
Answer: A. Address Latch Enable
Explanation:
ALE is used to demultiplex address/data lines (AD0–AD7).
37. The instruction “OUT 21H” performs:
A. Sends data from accumulator to I/O port 21H
B. Reads data from port 21H
C. Output program counter
D. Sends address to 21H
Answer: A. Sends data from accumulator to I/O port 21H
Explanation:
OUT transfers accumulator data to specified output port.
38. The flag register in 8085 is:
A. 8-bit
B. 16-bit
C. 4-bit
D. 10-bit
Answer: A. 8-bit
Explanation:
The flag register is 8-bit, of which 5 bits represent condition flags.
39. Which register is not accessible to the user?
A. Accumulator
B. Instruction Register
C. Stack Pointer
D. Program Counter
Answer: B. Instruction Register
Explanation:
Instruction Register is internal and not user accessible.
40. The machine cycle in which memory data is read is:
A. Opcode fetch
B. Memory read
C. Memory write
D. I/O write
Answer: B. Memory read
Explanation:
Memory read cycle reads data from memory into processor.
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