341. The instruction LXI H, 2050H loads
A. 2050H into accumulator
B. 2050H into HL register pair
C. Data at 2050H into H register
D. Data at 2050H into L register
Answer: B. 2050H into HL register pair
Explanation:
LXI H, 2050H loads the 16-bit data 2050H into HL pair directly.
342. The program counter (PC) is a
A. 8-bit register
B. 16-bit register
C. 32-bit register
D. 4-bit register
Answer: B. 16-bit register
Explanation:
The PC holds the 16-bit address of the next instruction to be executed.
343. The instruction MOV M, A transfers data to
A. Memory pointed by BC
B. Memory pointed by HL
C. Accumulator
D. Stack
Answer: B. Memory pointed by HL
Explanation:
Here M represents the memory location whose address is held in HL pair.
344. Which instruction clears accumulator content?
A. XRA A
B. MOV A, 00H
C. CMA
D. ANI 00H
Answer: A. XRA A
Explanation:
XRA A performs XOR of accumulator with itself → result = 00H.
345. The 8085 microprocessor has how many hardware interrupts?
A. 2
B. 3
C. 5
D. 8
Answer: C. 5
Explanation:
8085 has five hardware interrupts: TRAP, RST7.5, RST6.5, RST5.5, and INTR.
346. TRAP is a
A. Maskable interrupt
B. Non-maskable interrupt
C. Software interrupt
D. External interrupt only
Answer: B. Non-maskable interrupt
Explanation:
TRAP cannot be disabled; it has the highest priority among all interrupts.
347. The lowest priority interrupt in 8085 is
A. TRAP
B. RST 5.5
C. RST 6.5
D. INTR
Answer: D. INTR
Explanation:
INTR has the lowest priority and is a general-purpose external interrupt.
348. The instruction CMP B compares
A. A with B
B. B with A
C. A with memory
D. B with memory
Answer: A. A with B
Explanation:
CMP subtracts the content of B from A internally, sets flags but does not store result.
349. The instruction DAD H
A. Adds HL to HL
B. Adds H to A
C. Adds contents of H to L
D. Adds contents of DE to HL
Answer: A. Adds HL to HL
Explanation:
DAD H means HL = HL + HL (adds 16-bit data in HL pair to itself).
350. The instruction INX SP
A. Increments SP by 1
B. Increments SP by 2
C. Decrements SP by 1
D. Decrements SP by 2
Answer: B. Increments SP by 2
Explanation:
SP is a 16-bit register; INX SP increases it by 1 in each byte → 2 total.
351. The stack in 8085 grows
A. Upward
B. Downward
C. Both directions
D. Fixed location
Answer: B. Downward
Explanation:
The stack grows towards lower memory addresses (SP decrements when data is pushed).
352. The instruction PUSH PSW pushes
A. Only accumulator
B. Accumulator and flag register
C. Only flag register
D. HL pair
Answer: B. Accumulator and flag register
Explanation:
PSW = Program Status Word = Accumulator + Flag register.
353. The instruction POP PSW
A. Pops data into accumulator only
B. Pops data into accumulator and flag register
C. Pops data into flag register only
D. Pops data into memory
Answer: B. Accumulator and flag register
Explanation:
POP PSW restores accumulator and flags from the stack.
354. What is the size of opcode for MOV A, B?
A. 1 byte
B. 2 bytes
C. 3 bytes
D. 4 bytes
Answer: A. 1 byte
Explanation:
MOV instructions are single-byte since all information is in the opcode.
355. Which instruction does not affect any flag?
A. MOV A, B
B. ADD B
C. SUB B
D. INR A
Answer: A. MOV A, B
Explanation:
MOV just copies data; it does not modify or set any flag.
356. The instruction RLC means
A. Rotate left through carry
B. Rotate left without carry
C. Rotate right through carry
D. Rotate right without carry
Answer: B. Rotate left without carry
Explanation:
RLC rotates all bits of accumulator left; D7 moves to D0 and carry flag.
357. The instruction RAL means
A. Rotate accumulator left through carry
B. Rotate accumulator right
C. Rotate accumulator right through carry
D. Complement accumulator
Answer: A. Rotate accumulator left through carry
Explanation:
RAL rotates accumulator left using carry flag in the rotation.
358. How many T-states are used in MOV A, B?
A. 4
B. 7
C. 10
D. 5
Answer: A. 4
Explanation:
Simple register-to-register data transfer takes 4 T-states in 8085.
359. What is the function of ALE pin?
A. Latches lower address
B. Enables memory
C. Provides control signal
D. Indicates instruction fetch
Answer: A. Latches lower address
Explanation:
ALE (Address Latch Enable) separates address and data lines by latching lower address (A0–A7).
360. The 8085 instruction “NOP” means
A. Stop program
B. No operation
C. Hold execution
D. Null instruction
Answer: B. No operation
Explanation:
NOP performs no action but consumes one instruction cycle (4 T-states).
361. The signal IO/M̅ differentiates between
A. Read and Write
B. I/O and Memory operation
C. Data and Address
D. Instruction and Data
Answer: B. I/O and Memory operation
Explanation:
IO/M̅ = 0 → Memory operation, IO/M̅ = 1 → I/O operation.
362. Which instruction disables interrupts?
A. SIM
B. DI
C. EI
D. RIM
Answer: B. DI
Explanation:
DI (Disable Interrupts) masks all interrupt lines.
363. Which instruction enables interrupts?
A. RIM
B. SIM
C. EI
D. DI
Answer: C. EI
Explanation:
EI (Enable Interrupts) allows the processor to recognize hardware interrupts.
364. The instruction CMA does what?
A. Complements accumulator
B. Clears accumulator
C. Copies accumulator
D. Masks accumulator
Answer: A. Complements accumulator
Explanation:
CMA converts each bit of accumulator to its complement.
365. The instruction HLT causes
A. CPU to stop executing instructions
B. CPU to reset
C. CPU to go into standby
D. Program to restart
Answer: A. CPU to stop executing instructions
Explanation:
HLT halts the processor until reset or interrupt occurs.
366. The instruction SUI 08H means
A. Subtract 08H from accumulator
B. Add 08H to accumulator
C. Subtract accumulator from 08H
D. None
Answer: A. Subtract 08H from accumulator
Explanation:
SUI data subtracts immediate 8-bit data from the accumulator.
367. The instruction MVI A, 32H means
A. Move 32H to memory
B. Load accumulator with 32H
C. Move accumulator to 32H
D. Store A into 32H
Answer: B. Load accumulator with 32H
Explanation:
MVI A, data loads immediate data into accumulator.
368. The flag register has how many active flags?
A. 3
B. 5
C. 6
D. 8
Answer: B. 5
Explanation:
8085 has 5 active flags: S, Z, AC, P, CY.
369. The parity flag is set if
A. Number of 1s in result is even
B. Number of 1s in result is odd
C. Result is zero
D. Carry occurs
Answer: A. Number of 1s in result is even
Explanation:
Parity flag = 1 if even number of 1s in result.
370. The instruction ORA B
A. Logical AND with B
B. Logical OR with B
C. Add B
D. Compare B
Answer: B. Logical OR with B
Explanation:
ORA performs bitwise OR of accumulator with register B.
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