501. The 8085 has how many hardware interrupts?
A. 3
B. 4
C. 5
D. 6
Answer: C
Explanation:
8085 has 5 hardware interrupts — TRAP, RST7.5, RST6.5, RST5.5, INTR.
502. The highest priority interrupt in 8085 is:
A. RST 7.5
B. RST 6.5
C. TRAP
D. INTR
Answer: C
Explanation:
TRAP is non-maskable and has the highest priority among all interrupts.
503. The lowest priority interrupt in 8085 is:
A. RST 5.5
B. RST 7.5
C. INTR
D. TRAP
Answer: C
Explanation:
INTR is the lowest priority, maskable interrupt.
504. Which interrupt is non-maskable?
A. RST 5.5
B. RST 6.5
C. RST 7.5
D. TRAP
Answer: D
Explanation:
TRAP cannot be disabled by software; it’s non-maskable and edge + level triggered.
505. RST 7.5 is:
A. Edge triggered
B. Level triggered
C. Both edge and level
D. None
Answer: A
Explanation:
RST 7.5 is a positive edge-triggered interrupt.
506. RST 6.5 and RST 5.5 are:
A. Edge triggered
B. Level triggered
C. Both
D. None
Answer: B
Explanation:
RST 6.5 and RST 5.5 are level triggered maskable interrupts.
507. Which interrupt vector address corresponds to RST 7.5?
A. 003CH
B. 0034H
C. 003CH
D. 0030H
Answer: A
Explanation:
Each RST = 8 × N; for RST 7.5, address = 7.5 × 8 = 60 = 3CH.
508. The vector address of RST 6.5 is:
A. 0034H
B. 002CH
C. 003CH
D. 0024H
Answer: A
Explanation:
For RST 6.5 → 6.5 × 8 = 52 = 34H.
509. The EI instruction is used to:
A. Enable all interrupts
B. Disable all interrupts
C. Enable TRAP only
D. Enable RST 7.5 only
Answer: A
Explanation:
EI = Enable Interrupts. It sets the interrupt flip-flop to allow maskable interrupts.
510. The DI instruction is used to:
A. Disable interrupts
B. Enable interrupts
C. Disable only TRAP
D. None
Answer: A
Explanation:
DI = Disable Interrupts → clears the interrupt enable flip-flop.
511. The instruction SIM stands for:
A. Set Interrupt Mask
B. Software Interrupt Mask
C. Set Internal Memory
D. None
Answer: A
Explanation:
SIM controls interrupt masking and serial output via the accumulator bits.
512. The instruction RIM stands for:
A. Read Interrupt Mask
B. Reset Interrupt Mask
C. Read Input Memory
D. None
Answer: A
Explanation:
RIM reads the status of interrupt masks and serial input bit.
513. Which flag is affected by CMP instruction?
A. Carry
B. Zero
C. Sign
D. All of these
Answer: D
Explanation:
CMP affects Carry, Zero, Sign, and Parity flags according to subtraction result.
514. The accumulator contents after XRA A are:
A. 00H
B. FFH
C. A's complement
D. Unchanged
Answer: A
Explanation:
A XOR A = 00H → all flags reset except Zero = 1.
515. The instruction ORA B performs:
A. Bitwise OR
B. Bitwise AND
C. Bitwise XOR
D. Addition
Answer: A
Explanation:
ORA = Bitwise OR between accumulator and register.
516. The instruction ANI 0FH does what?
A. AND accumulator with 0FH
B. OR accumulator with 0FH
C. Add 0FH
D. None
Answer: A
Explanation:
ANI = Logical AND immediate → A = A & 0FH.
517. The instruction ORI 20H means:
A. OR accumulator with 20H
B. AND accumulator with 20H
C. XOR accumulator with 20H
D. Add 20H
Answer: A
Explanation:
ORI performs OR operation with immediate data.
518. Which instruction rotates accumulator left?
A. RAL
B. RLC
C. RAR
D. RRC
Answer: B
Explanation:
RLC rotates accumulator left through carry.
519. RAL differs from RLC by:
A. Including carry in rotation
B. Ignoring carry
C. Rotating right
D. None
Answer: A
Explanation:
RAL rotates accumulator left through carry, while RLC doesn’t use carry.
520. RAR rotates accumulator:
A. Right through carry
B. Left through carry
C. Right without carry
D. Left without carry
Answer: A
Explanation:
RAR = Rotate Accumulator Right through Carry.
521. The instruction PCHL performs:
A. Jump to address in HL pair
B. Push HL to stack
C. Load H and L from PC
D. None
Answer: A
Explanation:
PCHL → Load Program Counter with HL → jump indirectly.
522. The instruction SPHL performs:
A. Load Stack Pointer with HL contents
B. Load HL with SP
C. Swap HL and SP
D. None
Answer: A
Explanation:
SPHL → SP = HL.
523. The instruction XTHL exchanges:
A. HL ↔ Top of stack
B. HL ↔ BC
C. HL ↔ DE
D. HL ↔ Accumulator
Answer: A
Explanation:
XTHL exchanges top two bytes of stack with HL registers.
524. XCHG exchanges:
A. HL and DE
B. BC and DE
C. HL and BC
D. None
Answer: A
Explanation:
XCHG swaps content of HL ↔ DE pairs.
525. How many T-states does MOV A,B require?
A. 4
B. 7
C. 5
D. 10
Answer: A
Explanation:
MOV is a one-byte instruction; requires 4 T-states.
526. How many T-states does LDA 2050H require?
A. 13
B. 10
C. 7
D. 4
Answer: A
Explanation:
LDA is 3-byte instruction → needs 13 T-states.
527. How many T-states does STA 3000H require?
A. 13
B. 10
C. 4
D. 7
Answer: A
Explanation:
STA stores A into given address, 3 bytes → 13 T-states.
528. The instruction IN 05H needs how many bytes?
A. 1
B. 2
C. 3
D. None
Answer: B
Explanation:
IN and OUT are 2-byte I/O operations.
529. OUT 0AH transfers:
A. A → Port 0AH
B. Port 0AH → A
C. HL → Port 0AH
D. None
Answer: A
Explanation:
OUT sends accumulator data to output port address.
530. Stack grows:
A. Upward
B. Downward
C. Fixed
D. Random
Answer: B
Explanation:
In 8085, stack grows downward (higher → lower addresses).
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