371. The instruction ANA B performs
A. OR operation between A and B
B. AND operation between A and B
C. XOR operation
D. Addition of A and B
Answer: B. AND operation between A and B
Explanation:
ANA performs bitwise logical AND between accumulator and register B, storing the result in accumulator.
372. The instruction XRA B performs
A. Logical AND
B. Logical OR
C. Logical XOR
D. Logical NOT
Answer: C. Logical XOR
Explanation:
XRA performs bitwise exclusive OR between accumulator and register B.
373. The instruction ADI 09H performs
A. Adds 09H to accumulator
B. Subtracts 09H from accumulator
C. ANDs 09H with accumulator
D. Compares with 09H
Answer: A. Adds 09H to accumulator
Explanation:
ADI data is an immediate addition instruction.
374. The instruction SBB B performs
A. Subtracts B from accumulator with borrow
B. Subtracts accumulator from B
C. Subtracts B from accumulator without borrow
D. Adds accumulator to B
Answer: A. Subtracts B from accumulator with borrow
Explanation:
SBB = Subtract register + borrow flag from accumulator.
375. The instruction STAX B
A. Stores accumulator in memory pointed by BC
B. Stores accumulator in memory pointed by DE
C. Loads accumulator from memory pointed by BC
D. Exchanges A and B
Answer: A. Stores accumulator in memory pointed by BC
Explanation:
STAX stores accumulator content in the memory location whose address is in register pair B–C.
376. The instruction LDAX D
A. Loads accumulator from memory pointed by DE
B. Loads accumulator from memory pointed by BC
C. Stores accumulator into DE
D. Copies D into A
Answer: A. Loads accumulator from memory pointed by DE
Explanation:
LDAX loads accumulator with data from the memory address in register pair DE.
377. The instruction DCX B
A. Decrements B by 1
B. Decrements BC pair by 1
C. Decrements B by 2
D. Decrements memory content
Answer: B. Decrements BC pair by 1
Explanation:
DCX decrements the 16-bit content of a register pair by one.
378. Which of the following instructions does not affect flags?
A. DCR A
B. INX H
C. ADD B
D. SUI 01H
Answer: B. INX H
Explanation:
INX and DCX do not affect any flags because they operate on 16-bit register pairs.
379. The instruction JMP 2050H
A. Jumps to address 2050H unconditionally
B. Jumps if zero flag is set
C. Jumps if carry flag is set
D. Calls subroutine at 2050H
Answer: A. Jumps to address 2050H unconditionally
Explanation:
JMP performs an unconditional jump to the specified 16-bit address.
380. The instruction JC 3000H
A. Jumps if carry flag = 1
B. Jumps if carry flag = 0
C. Jumps always
D. Calls subroutine at 3000H
Answer: A. Jumps if carry flag = 1
Explanation:
JC = Jump if Carry; it is a conditional jump instruction.
381. The instruction JNC 2500H
A. Jumps if carry flag = 1
B. Jumps if carry flag = 0
C. Jumps if zero flag = 0
D. Jumps unconditionally
Answer: B. Jumps if carry flag = 0
Explanation:
JNC = Jump if No Carry.
382. The instruction JZ 2000H
A. Jumps if result = zero
B. Jumps if result ≠ zero
C. Jumps always
D. Jumps if carry = 1
Answer: A. Jumps if result = zero
Explanation:
JZ checks the Zero flag; if set, control transfers to 2000H.
383. The instruction JNZ 4000H
A. Jumps if zero flag = 0
B. Jumps if carry flag = 0
C. Jumps if sign flag = 1
D. Jumps always
Answer: A. Jumps if zero flag = 0
Explanation:
JNZ = Jump if Not Zero.
384. The instruction CALL 2080H
A. Jumps to 2080H without return
B. Calls subroutine at 2080H
C. Halts CPU
D. Restarts CPU
Answer: B. Calls subroutine at 2080H
Explanation:
CALL transfers control to the subroutine at the specified address, storing the return address on the stack.
385. The instruction RET
A. Returns from subroutine
B. Returns from interrupt
C. Restarts program
D. Ends program
Answer: A. Returns from subroutine
Explanation:
RET pops the return address from the stack and resumes execution.
386. The instruction RST 5
A. Restarts program at location 0028H
B. Restarts at 0024H
C. Restarts at 0020H
D. Restarts at 0030H
Answer: B. Restarts at 0028H
Explanation:
RST n = Call 8×n. For RST 5, 8×5 = 40 → 28H.
387. How many software interrupts are there in 8085?
A. 5
B. 8
C. 10
D. 4
Answer: B. 8
Explanation:
There are 8 software interrupts — RST 0 through RST 7.
388. The instruction EI
A. Enables interrupts
B. Disables interrupts
C. Executes interrupt
D. Ends interrupt
Answer: A. Enables interrupts
Explanation:
EI allows the CPU to accept maskable interrupts.
389. The instruction SIM
A. Sets interrupt mask
B. Reads interrupt mask
C. Stops interrupt
D. Enables TRAP
Answer: A. Sets interrupt mask
Explanation:
SIM (Set Interrupt Mask) controls RST 7.5, 6.5, 5.5 masks and serial output data.
390. The instruction RIM
A. Reads interrupt mask
B. Sets interrupt mask
C. Disables interrupts
D. Enables interrupts
Answer: A. Reads interrupt mask
Explanation:
RIM (Read Interrupt Mask) reads mask status and serial input data.
391. The signal S1 and S0 indicate
A. Interrupt type
B. Machine cycle status
C. Address bus status
D. Ready status
Answer: B. Machine cycle status
Explanation:
S1 and S0 denote the type of machine cycle (opcode fetch, memory read/write, etc.).
392. The READY pin is used to
A. Synchronize slow peripherals
B. Reset processor
C. Enable interrupts
D. Provide clock
Answer: A. Synchronize slow peripherals
Explanation:
READY indicates whether peripheral is ready for data transfer; if low, 8085 waits.
393. The HOLD signal is used to
A. Request bus control from processor
B. Stop CPU clock
C. Indicate power fail
D. Enable interrupts
Answer: A. Request bus control from processor
Explanation:
HOLD is used by DMA or other devices to take control of buses.
394. The HLDA signal means
A. Hold Acknowledge
B. Halt Done
C. Hardware Lock
D. High Logic Data Available
Answer: A. Hold Acknowledge
Explanation:
HLDA is sent by CPU to indicate it has granted the HOLD request.
395. The instruction XTHL
A. Exchanges top of stack with HL
B. Exchanges HL with DE
C. Exchanges accumulator with memory
D. Exchanges stack pointer with HL
Answer: A. Exchanges top of stack with HL
Explanation:
XTHL exchanges contents of L ↔ (SP), H ↔ (SP+1).
396. The instruction SPHL
A. Copies SP into HL
B. Copies HL into SP
C. Exchanges HL and SP
D. Decrements SP
Answer: B. Copies HL into SP
Explanation:
SPHL loads stack pointer with the content of HL register pair.
397. The instruction PCHL
A. Loads PC with HL content
B. Loads HL with PC content
C. Pushes PC to stack
D. Pops PC from stack
Answer: A. Loads PC with HL content
Explanation:
PCHL changes program counter to address in HL → acts as a jump.
398. The instruction DAA
A. Decimal Adjust Accumulator
B. Decrement Accumulator Again
C. Double Add Accumulator
D. Data Add Accumulator
Answer: A. Decimal Adjust Accumulator
Explanation:
DAA adjusts the accumulator for BCD operations after addition.
399. What is the maximum clock frequency of 8085?
A. 2 MHz
B. 3 MHz
C. 5 MHz
D. 8 MHz
Answer: C. 5 MHz
Explanation:
Standard 8085 operates up to 5 MHz; some versions at 6 MHz.
400. The addressing mode used in MOV A, M is
A. Immediate
B. Direct
C. Register
D. Register indirect
Answer: D. Register indirect
Explanation:
Here M refers to memory location pointed by HL pair → register indirect addressing.
No comments:
Post a Comment